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1da177e4 LT |
1 | /* |
2 | * include/asm-alpha/dma.h | |
3 | * | |
4 | * This is essentially the same as the i386 DMA stuff, as the AlphaPCs | |
5 | * use ISA-compatible dma. The only extension is support for high-page | |
6 | * registers that allow to set the top 8 bits of a 32-bit DMA address. | |
7 | * This register should be written last when setting up a DMA address | |
8 | * as this will also enable DMA across 64 KB boundaries. | |
9 | */ | |
10 | ||
11 | /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $ | |
12 | * linux/include/asm/dma.h: Defines for using and allocating dma channels. | |
13 | * Written by Hennus Bergman, 1992. | |
14 | * High DMA channel support & info by Hannu Savolainen | |
15 | * and John Boyd, Nov. 1992. | |
16 | */ | |
17 | ||
18 | #ifndef _ASM_DMA_H | |
19 | #define _ASM_DMA_H | |
20 | ||
21 | #include <linux/config.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <asm/io.h> | |
24 | ||
25 | #define dma_outb outb | |
26 | #define dma_inb inb | |
27 | ||
28 | /* | |
29 | * NOTES about DMA transfers: | |
30 | * | |
31 | * controller 1: channels 0-3, byte operations, ports 00-1F | |
32 | * controller 2: channels 4-7, word operations, ports C0-DF | |
33 | * | |
34 | * - ALL registers are 8 bits only, regardless of transfer size | |
35 | * - channel 4 is not used - cascades 1 into 2. | |
36 | * - channels 0-3 are byte - addresses/counts are for physical bytes | |
37 | * - channels 5-7 are word - addresses/counts are for physical words | |
38 | * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries | |
39 | * - transfer count loaded to registers is 1 less than actual count | |
40 | * - controller 2 offsets are all even (2x offsets for controller 1) | |
41 | * - page registers for 5-7 don't use data bit 0, represent 128K pages | |
42 | * - page registers for 0-3 use bit 0, represent 64K pages | |
43 | * | |
44 | * DMA transfers are limited to the lower 16MB of _physical_ memory. | |
45 | * Note that addresses loaded into registers must be _physical_ addresses, | |
46 | * not logical addresses (which may differ if paging is active). | |
47 | * | |
48 | * Address mapping for channels 0-3: | |
49 | * | |
50 | * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) | |
51 | * | ... | | ... | | ... | | |
52 | * | ... | | ... | | ... | | |
53 | * | ... | | ... | | ... | | |
54 | * P7 ... P0 A7 ... A0 A7 ... A0 | |
55 | * | Page | Addr MSB | Addr LSB | (DMA registers) | |
56 | * | |
57 | * Address mapping for channels 5-7: | |
58 | * | |
59 | * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) | |
60 | * | ... | \ \ ... \ \ \ ... \ \ | |
61 | * | ... | \ \ ... \ \ \ ... \ (not used) | |
62 | * | ... | \ \ ... \ \ \ ... \ | |
63 | * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 | |
64 | * | Page | Addr MSB | Addr LSB | (DMA registers) | |
65 | * | |
66 | * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses | |
67 | * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at | |
68 | * the hardware level, so odd-byte transfers aren't possible). | |
69 | * | |
70 | * Transfer count (_not # bytes_) is limited to 64K, represented as actual | |
71 | * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, | |
72 | * and up to 128K bytes may be transferred on channels 5-7 in one operation. | |
73 | * | |
74 | */ | |
75 | ||
76 | #define MAX_DMA_CHANNELS 8 | |
77 | ||
78 | /* | |
79 | ISA DMA limitations on Alpha platforms, | |
80 | ||
81 | These may be due to SIO (PCI<->ISA bridge) chipset limitation, or | |
82 | just a wiring limit. | |
83 | */ | |
84 | ||
85 | /* The maximum address for ISA DMA transfer on Alpha XL, due to an | |
86 | hardware SIO limitation, is 64MB. | |
87 | */ | |
88 | #define ALPHA_XL_MAX_ISA_DMA_ADDRESS 0x04000000UL | |
89 | ||
90 | /* The maximum address for ISA DMA transfer on RUFFIAN, | |
91 | due to an hardware SIO limitation, is 16MB. | |
92 | */ | |
93 | #define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS 0x01000000UL | |
94 | ||
95 | /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs, | |
96 | due to an hardware SIO chip limitation, is 2GB. | |
97 | */ | |
98 | #define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS 0x80000000UL | |
99 | #define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS 0x80000000UL | |
100 | ||
101 | /* | |
102 | Maximum address for all the others is the complete 32-bit bus | |
103 | address space. | |
104 | */ | |
105 | #define ALPHA_MAX_ISA_DMA_ADDRESS 0x100000000UL | |
106 | ||
107 | #ifdef CONFIG_ALPHA_GENERIC | |
108 | # define MAX_ISA_DMA_ADDRESS (alpha_mv.max_isa_dma_address) | |
109 | #else | |
110 | # if defined(CONFIG_ALPHA_XL) | |
111 | # define MAX_ISA_DMA_ADDRESS ALPHA_XL_MAX_ISA_DMA_ADDRESS | |
112 | # elif defined(CONFIG_ALPHA_RUFFIAN) | |
113 | # define MAX_ISA_DMA_ADDRESS ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS | |
114 | # elif defined(CONFIG_ALPHA_SABLE) | |
115 | # define MAX_ISA_DMA_ADDRESS ALPHA_SABLE_MAX_ISA_DMA_ADDRESS | |
116 | # elif defined(CONFIG_ALPHA_ALCOR) | |
117 | # define MAX_ISA_DMA_ADDRESS ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS | |
118 | # else | |
119 | # define MAX_ISA_DMA_ADDRESS ALPHA_MAX_ISA_DMA_ADDRESS | |
120 | # endif | |
121 | #endif | |
122 | ||
123 | /* If we have the iommu, we don't have any address limitations on DMA. | |
124 | Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone | |
125 | like i386. */ | |
126 | #define MAX_DMA_ADDRESS (alpha_mv.mv_pci_tbi ? \ | |
127 | ~0UL : IDENT_ADDR + 0x01000000) | |
128 | ||
129 | /* 8237 DMA controllers */ | |
130 | #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ | |
131 | #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ | |
132 | ||
133 | /* DMA controller registers */ | |
134 | #define DMA1_CMD_REG 0x08 /* command register (w) */ | |
135 | #define DMA1_STAT_REG 0x08 /* status register (r) */ | |
136 | #define DMA1_REQ_REG 0x09 /* request register (w) */ | |
137 | #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ | |
138 | #define DMA1_MODE_REG 0x0B /* mode register (w) */ | |
139 | #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ | |
140 | #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ | |
141 | #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ | |
142 | #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ | |
143 | #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ | |
144 | #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) | |
145 | ||
146 | #define DMA2_CMD_REG 0xD0 /* command register (w) */ | |
147 | #define DMA2_STAT_REG 0xD0 /* status register (r) */ | |
148 | #define DMA2_REQ_REG 0xD2 /* request register (w) */ | |
149 | #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ | |
150 | #define DMA2_MODE_REG 0xD6 /* mode register (w) */ | |
151 | #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ | |
152 | #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ | |
153 | #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ | |
154 | #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ | |
155 | #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ | |
156 | #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) | |
157 | ||
158 | #define DMA_ADDR_0 0x00 /* DMA address registers */ | |
159 | #define DMA_ADDR_1 0x02 | |
160 | #define DMA_ADDR_2 0x04 | |
161 | #define DMA_ADDR_3 0x06 | |
162 | #define DMA_ADDR_4 0xC0 | |
163 | #define DMA_ADDR_5 0xC4 | |
164 | #define DMA_ADDR_6 0xC8 | |
165 | #define DMA_ADDR_7 0xCC | |
166 | ||
167 | #define DMA_CNT_0 0x01 /* DMA count registers */ | |
168 | #define DMA_CNT_1 0x03 | |
169 | #define DMA_CNT_2 0x05 | |
170 | #define DMA_CNT_3 0x07 | |
171 | #define DMA_CNT_4 0xC2 | |
172 | #define DMA_CNT_5 0xC6 | |
173 | #define DMA_CNT_6 0xCA | |
174 | #define DMA_CNT_7 0xCE | |
175 | ||
176 | #define DMA_PAGE_0 0x87 /* DMA page registers */ | |
177 | #define DMA_PAGE_1 0x83 | |
178 | #define DMA_PAGE_2 0x81 | |
179 | #define DMA_PAGE_3 0x82 | |
180 | #define DMA_PAGE_5 0x8B | |
181 | #define DMA_PAGE_6 0x89 | |
182 | #define DMA_PAGE_7 0x8A | |
183 | ||
184 | #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0) | |
185 | #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1) | |
186 | #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2) | |
187 | #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3) | |
188 | #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4) | |
189 | #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5) | |
190 | #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6) | |
191 | #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7) | |
192 | ||
193 | #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ | |
194 | #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ | |
195 | #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ | |
196 | ||
197 | #define DMA_AUTOINIT 0x10 | |
198 | ||
199 | extern spinlock_t dma_spin_lock; | |
200 | ||
201 | static __inline__ unsigned long claim_dma_lock(void) | |
202 | { | |
203 | unsigned long flags; | |
204 | spin_lock_irqsave(&dma_spin_lock, flags); | |
205 | return flags; | |
206 | } | |
207 | ||
208 | static __inline__ void release_dma_lock(unsigned long flags) | |
209 | { | |
210 | spin_unlock_irqrestore(&dma_spin_lock, flags); | |
211 | } | |
212 | ||
213 | /* enable/disable a specific DMA channel */ | |
214 | static __inline__ void enable_dma(unsigned int dmanr) | |
215 | { | |
216 | if (dmanr<=3) | |
217 | dma_outb(dmanr, DMA1_MASK_REG); | |
218 | else | |
219 | dma_outb(dmanr & 3, DMA2_MASK_REG); | |
220 | } | |
221 | ||
222 | static __inline__ void disable_dma(unsigned int dmanr) | |
223 | { | |
224 | if (dmanr<=3) | |
225 | dma_outb(dmanr | 4, DMA1_MASK_REG); | |
226 | else | |
227 | dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); | |
228 | } | |
229 | ||
230 | /* Clear the 'DMA Pointer Flip Flop'. | |
231 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | |
232 | * Use this once to initialize the FF to a known state. | |
233 | * After that, keep track of it. :-) | |
234 | * --- In order to do that, the DMA routines below should --- | |
235 | * --- only be used while interrupts are disabled! --- | |
236 | */ | |
237 | static __inline__ void clear_dma_ff(unsigned int dmanr) | |
238 | { | |
239 | if (dmanr<=3) | |
240 | dma_outb(0, DMA1_CLEAR_FF_REG); | |
241 | else | |
242 | dma_outb(0, DMA2_CLEAR_FF_REG); | |
243 | } | |
244 | ||
245 | /* set mode (above) for a specific DMA channel */ | |
246 | static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | |
247 | { | |
248 | if (dmanr<=3) | |
249 | dma_outb(mode | dmanr, DMA1_MODE_REG); | |
250 | else | |
251 | dma_outb(mode | (dmanr&3), DMA2_MODE_REG); | |
252 | } | |
253 | ||
254 | /* set extended mode for a specific DMA channel */ | |
255 | static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode) | |
256 | { | |
257 | if (dmanr<=3) | |
258 | dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG); | |
259 | else | |
260 | dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG); | |
261 | } | |
262 | ||
263 | /* Set only the page register bits of the transfer address. | |
264 | * This is used for successive transfers when we know the contents of | |
265 | * the lower 16 bits of the DMA current address register. | |
266 | */ | |
267 | static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr) | |
268 | { | |
269 | switch(dmanr) { | |
270 | case 0: | |
271 | dma_outb(pagenr, DMA_PAGE_0); | |
272 | dma_outb((pagenr >> 8), DMA_HIPAGE_0); | |
273 | break; | |
274 | case 1: | |
275 | dma_outb(pagenr, DMA_PAGE_1); | |
276 | dma_outb((pagenr >> 8), DMA_HIPAGE_1); | |
277 | break; | |
278 | case 2: | |
279 | dma_outb(pagenr, DMA_PAGE_2); | |
280 | dma_outb((pagenr >> 8), DMA_HIPAGE_2); | |
281 | break; | |
282 | case 3: | |
283 | dma_outb(pagenr, DMA_PAGE_3); | |
284 | dma_outb((pagenr >> 8), DMA_HIPAGE_3); | |
285 | break; | |
286 | case 5: | |
287 | dma_outb(pagenr & 0xfe, DMA_PAGE_5); | |
288 | dma_outb((pagenr >> 8), DMA_HIPAGE_5); | |
289 | break; | |
290 | case 6: | |
291 | dma_outb(pagenr & 0xfe, DMA_PAGE_6); | |
292 | dma_outb((pagenr >> 8), DMA_HIPAGE_6); | |
293 | break; | |
294 | case 7: | |
295 | dma_outb(pagenr & 0xfe, DMA_PAGE_7); | |
296 | dma_outb((pagenr >> 8), DMA_HIPAGE_7); | |
297 | break; | |
298 | } | |
299 | } | |
300 | ||
301 | ||
302 | /* Set transfer address & page bits for specific DMA channel. | |
303 | * Assumes dma flipflop is clear. | |
304 | */ | |
305 | static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) | |
306 | { | |
307 | if (dmanr <= 3) { | |
308 | dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); | |
309 | dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); | |
310 | } else { | |
311 | dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); | |
312 | dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); | |
313 | } | |
314 | set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */ | |
315 | } | |
316 | ||
317 | ||
318 | /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for | |
319 | * a specific DMA channel. | |
320 | * You must ensure the parameters are valid. | |
321 | * NOTE: from a manual: "the number of transfers is one more | |
322 | * than the initial word count"! This is taken into account. | |
323 | * Assumes dma flip-flop is clear. | |
324 | * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. | |
325 | */ | |
326 | static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) | |
327 | { | |
328 | count--; | |
329 | if (dmanr <= 3) { | |
330 | dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); | |
331 | dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); | |
332 | } else { | |
333 | dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); | |
334 | dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); | |
335 | } | |
336 | } | |
337 | ||
338 | ||
339 | /* Get DMA residue count. After a DMA transfer, this | |
340 | * should return zero. Reading this while a DMA transfer is | |
341 | * still in progress will return unpredictable results. | |
342 | * If called before the channel has been used, it may return 1. | |
343 | * Otherwise, it returns the number of _bytes_ left to transfer. | |
344 | * | |
345 | * Assumes DMA flip-flop is clear. | |
346 | */ | |
347 | static __inline__ int get_dma_residue(unsigned int dmanr) | |
348 | { | |
349 | unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE | |
350 | : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; | |
351 | ||
352 | /* using short to get 16-bit wrap around */ | |
353 | unsigned short count; | |
354 | ||
355 | count = 1 + dma_inb(io_port); | |
356 | count += dma_inb(io_port) << 8; | |
357 | ||
358 | return (dmanr<=3)? count : (count<<1); | |
359 | } | |
360 | ||
361 | ||
362 | /* These are in kernel/dma.c: */ | |
363 | extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ | |
364 | extern void free_dma(unsigned int dmanr); /* release it again */ | |
365 | #define KERNEL_HAVE_CHECK_DMA | |
366 | extern int check_dma(unsigned int dmanr); | |
367 | ||
368 | /* From PCI */ | |
369 | ||
370 | #ifdef CONFIG_PCI | |
371 | extern int isa_dma_bridge_buggy; | |
372 | #else | |
373 | #define isa_dma_bridge_buggy (0) | |
374 | #endif | |
375 | ||
376 | ||
377 | #endif /* _ASM_DMA_H */ |