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1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/arch-h720x/h7202-regs.h | |
3 | * | |
4 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | |
5 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | |
6 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | |
7 | * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de> | |
8 | * | |
9 | * This file contains the hardware definitions of the h720x processors | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * Do not add implementations specific defines here. This files contains | |
16 | * only defines of the onchip peripherals. Add those defines to boards.h, | |
17 | * which is included by this file. | |
18 | */ | |
19 | ||
20 | #define SERIAL2_OFS 0x2d000 | |
21 | #define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS) | |
22 | #define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS) | |
23 | #define SERIAL3_OFS 0x2e000 | |
24 | #define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS) | |
25 | #define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS) | |
26 | ||
27 | /* Matrix Keyboard Controller */ | |
28 | #define KBD_VIRT (IO_VIRT + 0x22000) | |
29 | #define KBD_KBCR 0x00 | |
30 | #define KBD_KBSC 0x04 | |
31 | #define KBD_KBTR 0x08 | |
32 | #define KBD_KBVR0 0x0C | |
33 | #define KBD_KBVR1 0x10 | |
34 | #define KBD_KBSR 0x18 | |
35 | ||
36 | #define KBD_KBCR_SCANENABLE (1 << 7) | |
37 | #define KBD_KBCR_NPOWERDOWN (1 << 2) | |
38 | #define KBD_KBCR_CLKSEL_MASK (3) | |
39 | #define KBD_KBCR_CLKSEL_PCLK2 0x0 | |
40 | #define KBD_KBCR_CLKSEL_PCLK128 0x1 | |
41 | #define KBD_KBCR_CLKSEL_PCLK256 0x2 | |
42 | #define KBD_KBCR_CLKSEL_PCLK512 0x3 | |
43 | ||
44 | #define KBD_KBSR_INTR (1 << 0) | |
45 | #define KBD_KBSR_WAKEUP (1 << 1) | |
46 | ||
47 | /* USB device controller */ | |
48 | ||
49 | #define USBD_BASE (IO_VIRT + 0x12000) | |
50 | #define USBD_LENGTH 0x3C | |
51 | ||
52 | #define USBD_GCTRL 0x00 | |
53 | #define USBD_EPCTRL 0x04 | |
54 | #define USBD_INTMASK 0x08 | |
55 | #define USBD_INTSTAT 0x0C | |
56 | #define USBD_PWR 0x10 | |
57 | #define USBD_DMARXTX 0x14 | |
58 | #define USBD_DEVID 0x18 | |
59 | #define USBD_DEVCLASS 0x1C | |
60 | #define USBD_INTCLASS 0x20 | |
61 | #define USBD_SETUP0 0x24 | |
62 | #define USBD_SETUP1 0x28 | |
63 | #define USBD_ENDP0RD 0x2C | |
64 | #define USBD_ENDP0WT 0x30 | |
65 | #define USBD_ENDP1RD 0x34 | |
66 | #define USBD_ENDP2WT 0x38 | |
67 | ||
68 | /* PS/2 port */ | |
69 | #define PSDATA 0x00 | |
70 | #define PSSTAT 0x04 | |
71 | #define PSSTAT_TXEMPTY (1<<0) | |
72 | #define PSSTAT_TXBUSY (1<<1) | |
73 | #define PSSTAT_RXFULL (1<<2) | |
74 | #define PSSTAT_RXBUSY (1<<3) | |
75 | #define PSSTAT_CLKIN (1<<4) | |
76 | #define PSSTAT_DATAIN (1<<5) | |
77 | #define PSSTAT_PARITY (1<<6) | |
78 | ||
79 | #define PSCONF 0x08 | |
80 | #define PSCONF_ENABLE (1<<0) | |
81 | #define PSCONF_TXINTEN (1<<2) | |
82 | #define PSCONF_RXINTEN (1<<3) | |
83 | #define PSCONF_FORCECLKLOW (1<<4) | |
84 | #define PSCONF_FORCEDATLOW (1<<5) | |
85 | #define PSCONF_LCE (1<<6) | |
86 | ||
87 | #define PSINTR 0x0C | |
88 | #define PSINTR_TXINT (1<<0) | |
89 | #define PSINTR_RXINT (1<<1) | |
90 | #define PSINTR_PAR (1<<2) | |
91 | #define PSINTR_RXTO (1<<3) | |
92 | #define PSINTR_TXTO (1<<4) | |
93 | ||
94 | #define PSTDLO 0x10 /* clk low before start transmission */ | |
95 | #define PSTPRI 0x14 /* PRI clock */ | |
96 | #define PSTXMT 0x18 /* maximum transmission time */ | |
97 | #define PSTREC 0x20 /* maximum receive time */ | |
98 | #define PSPWDN 0x3c | |
99 | ||
100 | /* ADC converter */ | |
101 | #define ADC_BASE (IO_VIRT + 0x29000) | |
102 | #define ADC_CR 0x00 | |
103 | #define ADC_TSCTRL 0x04 | |
104 | #define ADC_BT_CTRL 0x08 | |
105 | #define ADC_MC_CTRL 0x0C | |
106 | #define ADC_STATUS 0x10 | |
107 | ||
108 | /* ADC control register bits */ | |
109 | #define ADC_CR_PW_CTRL 0x80 | |
110 | #define ADC_CR_DIRECTC 0x04 | |
111 | #define ADC_CR_CONTIME_NO 0x00 | |
112 | #define ADC_CR_CONTIME_2 0x04 | |
113 | #define ADC_CR_CONTIME_4 0x08 | |
114 | #define ADC_CR_CONTIME_ADE 0x0c | |
115 | #define ADC_CR_LONGCALTIME 0x01 | |
116 | ||
117 | /* ADC touch panel register bits */ | |
118 | #define ADC_TSCTRL_ENABLE 0x80 | |
119 | #define ADC_TSCTRL_INTR 0x40 | |
120 | #define ADC_TSCTRL_SWBYPSS 0x20 | |
121 | #define ADC_TSCTRL_SWINVT 0x10 | |
122 | #define ADC_TSCTRL_S400 0x03 | |
123 | #define ADC_TSCTRL_S200 0x02 | |
124 | #define ADC_TSCTRL_S100 0x01 | |
125 | #define ADC_TSCTRL_S50 0x00 | |
126 | ||
127 | /* ADC Interrupt Status Register bits */ | |
128 | #define ADC_STATUS_TS_BIT 0x80 | |
129 | #define ADC_STATUS_MBT_BIT 0x40 | |
130 | #define ADC_STATUS_BBT_BIT 0x20 | |
131 | #define ADC_STATUS_MIC_BIT 0x10 | |
132 | ||
133 | /* Touch data registers */ | |
134 | #define ADC_TS_X0X1 0x30 | |
135 | #define ADC_TS_X2X3 0x34 | |
136 | #define ADC_TS_Y0Y1 0x38 | |
137 | #define ADC_TS_Y2Y3 0x3c | |
138 | #define ADC_TS_X4X5 0x40 | |
139 | #define ADC_TS_X6X7 0x44 | |
140 | #define ADC_TS_Y4Y5 0x48 | |
141 | #define ADC_TS_Y6Y7 0x50 | |
142 | ||
143 | /* battery data */ | |
144 | #define ADC_MB_DATA 0x54 | |
145 | #define ADC_BB_DATA 0x58 | |
146 | ||
147 | /* Sound data register */ | |
148 | #define ADC_SD_DAT0 0x60 | |
149 | #define ADC_SD_DAT1 0x64 | |
150 | #define ADC_SD_DAT2 0x68 | |
151 | #define ADC_SD_DAT3 0x6c | |
152 | #define ADC_SD_DAT4 0x70 | |
153 | #define ADC_SD_DAT5 0x74 | |
154 | #define ADC_SD_DAT6 0x78 | |
155 | #define ADC_SD_DAT7 0x7c |