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c4713074 LB |
1 | /* |
2 | * include/asm-arm/arch-ixp23xx/ixp23xx.h | |
3 | * | |
4 | * Register definitions for IXP23XX | |
5 | * | |
6 | * Copyright (C) 2003-2005 Intel Corporation. | |
7 | * Copyright (C) 2005 MontaVista Software, Inc. | |
8 | * | |
9 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #ifndef __ASM_ARCH_IXP23XX_H | |
17 | #define __ASM_ARCH_IXP23XX_H | |
18 | ||
19 | /* | |
20 | * IXP2300 linux memory map: | |
21 | * | |
22 | * virt phys size | |
23 | * fffd0000 a0000000 64K XSI2CPP_CSR | |
24 | * fffc0000 c4000000 4K EXP_CFG | |
25 | * fff00000 c8000000 64K PERIPHERAL | |
26 | * fe000000 1c0000000 16M CAP_CSR | |
27 | * fd000000 1c8000000 16M MSF_CSR | |
28 | * fb000000 16M --- | |
29 | * fa000000 1d8000000 32M PCI_IO | |
30 | * f8000000 1da000000 32M PCI_CFG | |
31 | * f6000000 1de000000 32M PCI_CREG | |
32 | * f4000000 32M --- | |
33 | * f0000000 1e0000000 64M PCI_MEM | |
34 | * e[c-f]000000 per-platform mappings | |
35 | */ | |
36 | ||
37 | ||
38 | /**************************************************************************** | |
39 | * Static mappings. | |
40 | ****************************************************************************/ | |
41 | #define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000 | |
42 | #define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000 | |
43 | #define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000 | |
44 | ||
45 | #define IXP23XX_EXP_CFG_PHYS 0xc4000000 | |
46 | #define IXP23XX_EXP_CFG_VIRT 0xfffc0000 | |
47 | #define IXP23XX_EXP_CFG_SIZE 0x00001000 | |
48 | ||
49 | #define IXP23XX_PERIPHERAL_PHYS 0xc8000000 | |
50 | #define IXP23XX_PERIPHERAL_VIRT 0xfff00000 | |
51 | #define IXP23XX_PERIPHERAL_SIZE 0x00010000 | |
52 | ||
53 | #define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL | |
54 | #define IXP23XX_CAP_CSR_VIRT 0xfe000000 | |
55 | #define IXP23XX_CAP_CSR_SIZE 0x01000000 | |
56 | ||
57 | #define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL | |
58 | #define IXP23XX_MSF_CSR_VIRT 0xfd000000 | |
59 | #define IXP23XX_MSF_CSR_SIZE 0x01000000 | |
60 | ||
61 | #define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL | |
62 | #define IXP23XX_PCI_IO_VIRT 0xfa000000 | |
63 | #define IXP23XX_PCI_IO_SIZE 0x02000000 | |
64 | ||
65 | #define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL | |
66 | #define IXP23XX_PCI_CFG_VIRT 0xf8000000 | |
67 | #define IXP23XX_PCI_CFG_SIZE 0x02000000 | |
68 | #define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT | |
69 | #define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000) | |
70 | ||
71 | #define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL | |
72 | #define IXP23XX_PCI_CREG_VIRT 0xf6000000 | |
73 | #define IXP23XX_PCI_CREG_SIZE 0x02000000 | |
74 | #define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000) | |
75 | ||
76 | #define IXP23XX_PCI_MEM_START 0xe0000000 | |
77 | #define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL | |
78 | #define IXP23XX_PCI_MEM_VIRT 0xf0000000 | |
79 | #define IXP23XX_PCI_MEM_SIZE 0x04000000 | |
80 | ||
81 | ||
82 | /**************************************************************************** | |
83 | * XSI2CPP CSRs. | |
84 | ****************************************************************************/ | |
85 | #define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x))) | |
86 | #define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8) | |
87 | #define IXP23XX_CPP2XSI_ADDR_31 (1 << 19) | |
88 | #define IXP23XX_CPP2XSI_PSH_OFF (1 << 20) | |
89 | #define IXP23XX_CPP2XSI_COH_OFF (1 << 21) | |
90 | ||
91 | ||
92 | /**************************************************************************** | |
93 | * Expansion Bus Config. | |
94 | ****************************************************************************/ | |
95 | #define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x))) | |
96 | #define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00) | |
97 | #define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04) | |
98 | #define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08) | |
99 | #define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c) | |
100 | #define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10) | |
101 | #define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14) | |
102 | #define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18) | |
103 | #define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c) | |
104 | #define IXP23XX_FLASH_WRITABLE (0x2) | |
105 | #define IXP23XX_FLASH_BUS8 (0x1) | |
106 | ||
107 | #define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20) | |
108 | #define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24) | |
109 | #define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31) | |
110 | #define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22) | |
111 | #define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21) | |
112 | #define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19) | |
113 | #define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18) | |
114 | #define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16) | |
115 | #define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14) | |
116 | #define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13) | |
117 | #define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12) | |
118 | #define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5) | |
119 | #define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4) | |
120 | #define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3) | |
121 | #define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2) | |
122 | #define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1) | |
123 | #define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0) | |
124 | ||
125 | #define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28) | |
126 | #define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30) | |
8b76a68c | 127 | #define IXP23XX_EXP_CFG_FUSE IXP23XX_EXP_CFG_REG(0x34) |
c4713074 LB |
128 | |
129 | #define IXP23XX_EXP_BUS_PHYS 0x90000000 | |
130 | #define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000 | |
131 | ||
132 | #define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000) | |
133 | #define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000) | |
134 | #define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000) | |
135 | #define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000) | |
136 | #define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000) | |
137 | #define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000) | |
138 | #define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000) | |
139 | #define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000) | |
140 | ||
141 | ||
142 | /**************************************************************************** | |
143 | * Peripherals. | |
144 | ****************************************************************************/ | |
145 | #define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000) | |
146 | #define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000) | |
147 | #define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000) | |
148 | #define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000) | |
149 | #define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000) | |
150 | #define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000) | |
151 | #define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000) | |
152 | #define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000) | |
153 | #define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000) | |
154 | #define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000) | |
155 | #define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000) | |
156 | #define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000) | |
157 | #define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000) | |
158 | #define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000) | |
159 | ||
160 | #define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000) | |
161 | #define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000) | |
162 | #define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000) | |
163 | #define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000) | |
164 | #define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000) | |
165 | #define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000) | |
166 | #define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000) | |
167 | #define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000) | |
168 | #define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000) | |
169 | #define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000) | |
170 | #define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000) | |
171 | #define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000) | |
172 | #define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000) | |
173 | #define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000) | |
174 | ||
175 | ||
176 | /**************************************************************************** | |
177 | * Interrupt controller. | |
178 | ****************************************************************************/ | |
179 | #define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x))) | |
180 | #define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00) | |
181 | #define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04) | |
182 | #define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08) | |
183 | #define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c) | |
184 | #define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10) | |
185 | #define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14) | |
186 | #define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18) | |
187 | #define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c) | |
188 | #define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20) | |
189 | #define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24) | |
190 | #define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28) | |
191 | #define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c) | |
192 | #define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30) | |
193 | #define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34) | |
194 | #define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38) | |
195 | #define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c) | |
196 | #define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54 | |
197 | ||
198 | ||
199 | /**************************************************************************** | |
200 | * GPIO. | |
201 | ****************************************************************************/ | |
202 | #define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x))) | |
203 | #define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00) | |
204 | #define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04) | |
205 | #define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08) | |
206 | #define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c) | |
207 | #define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10) | |
208 | #define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14) | |
209 | #define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18) | |
210 | #define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c) | |
211 | ||
212 | #define IXP23XX_GPIO_STYLE_MASK 0x7 | |
213 | #define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0 | |
214 | #define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1 | |
215 | #define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2 | |
216 | #define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3 | |
217 | #define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4 | |
218 | ||
219 | #define IXP23XX_GPIO_STYLE_SIZE 3 | |
220 | ||
221 | ||
222 | /**************************************************************************** | |
223 | * Timer. | |
224 | ****************************************************************************/ | |
225 | #define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x))) | |
226 | #define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00) | |
227 | #define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04) | |
228 | #define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08) | |
229 | #define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c) | |
230 | #define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10) | |
231 | #define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14) | |
232 | #define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18) | |
233 | #define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c) | |
234 | #define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e | |
235 | #define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20) | |
236 | #define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24) | |
237 | #define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28) | |
238 | ||
239 | #define IXP23XX_TIMER_ENABLE (1 << 0) | |
240 | #define IXP23XX_TIMER_ONE_SHOT (1 << 1) | |
241 | /* Low order bits of reload value ignored */ | |
242 | #define IXP23XX_TIMER_RELOAD_MASK (0x3) | |
243 | #define IXP23XX_TIMER_DISABLED (0x0) | |
244 | #define IXP23XX_TIMER1_INT_PEND (1 << 0) | |
245 | #define IXP23XX_TIMER2_INT_PEND (1 << 1) | |
246 | #define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2) | |
247 | #define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3) | |
248 | #define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4) | |
249 | ||
250 | ||
251 | /**************************************************************************** | |
252 | * CAP CSRs. | |
253 | ****************************************************************************/ | |
254 | #define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x))) | |
e6fea6a5 | 255 | #define IXP23XX_PRODUCT_ID IXP23XX_GLOBAL_REG(0x00) |
c4713074 LB |
256 | #define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04) |
257 | #define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08) | |
258 | #define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c) | |
259 | #define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10) | |
260 | #define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18) | |
261 | ||
262 | #define IXP23XX_ENABLE_WATCHDOG (1 << 24) | |
263 | #define IXP23XX_SHPC_INIT_COMP (1 << 21) | |
264 | #define IXP23XX_RST_ALL (1 << 16) | |
265 | #define IXP23XX_RESET_PCI (1 << 2) | |
266 | #define IXP23XX_PCI_UNIT_RESET (1 << 1) | |
267 | #define IXP23XX_XSCALE_RESET (1 << 0) | |
268 | ||
8b76a68c LB |
269 | #define IXP23XX_UENGINE_CSR_VIRT_BASE (IXP23XX_CAP_CSR_VIRT + 0x18000) |
270 | ||
c4713074 LB |
271 | |
272 | /**************************************************************************** | |
273 | * PCI CSRs. | |
274 | ****************************************************************************/ | |
275 | #define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x))) | |
276 | #define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04) | |
277 | #define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14) | |
278 | #define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18) | |
279 | ||
280 | ||
281 | #define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x))) | |
282 | #define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030) | |
283 | #define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034) | |
284 | #define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc) | |
285 | #define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100) | |
286 | #define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c) | |
287 | #define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140) | |
288 | #define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148) | |
289 | #define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c) | |
290 | #define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150) | |
291 | #define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150) | |
292 | #define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154) | |
293 | #define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158) | |
294 | #define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c) | |
295 | #define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160) | |
296 | ||
297 | ||
c4713074 | 298 | #endif |