projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a7918f39 AZ |
1 | /* |
| 2 | * include/asm-arm/arch-ixp4xx/nslu2.h | |
| 3 | * | |
| 4 | * NSLU2 platform specific definitions | |
| 5 | * | |
| 6 | * Author: Mark Rakes <mrakes AT mac.com> | |
| 7 | * Maintainers: http://www.nslu2-linux.org | |
| 8 | * | |
| 9 | * based on ixdp425.h: | |
| 10 | * Copyright 2004 (c) MontaVista, Software, Inc. | |
| 11 | * | |
| 12 | * This file is licensed under the terms of the GNU General Public | |
| 13 | * License version 2. This program is licensed "as is" without any | |
| 14 | * warranty of any kind, whether express or implied. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef __ASM_ARCH_HARDWARE_H__ | |
| 18 | #error "Do not include this directly, instead #include <asm/hardware.h>" | |
| 19 | #endif | |
| 20 | ||
| a7918f39 AZ |
21 | #define NSLU2_SDA_PIN 7 |
| 22 | #define NSLU2_SCL_PIN 6 | |
| 23 | ||
| 24 | /* | |
| 25 | * NSLU2 PCI IRQs | |
| 26 | */ | |
| 27 | #define NSLU2_PCI_MAX_DEV 3 | |
| 28 | #define NSLU2_PCI_IRQ_LINES 3 | |
| 29 | ||
| 30 | ||
| 31 | /* PCI controller GPIO to IRQ pin mappings */ | |
| 32 | #define NSLU2_PCI_INTA_PIN 11 | |
| 33 | #define NSLU2_PCI_INTB_PIN 10 | |
| 34 | #define NSLU2_PCI_INTC_PIN 9 | |
| 35 | #define NSLU2_PCI_INTD_PIN 8 | |
| 36 | ||
| 37 | ||
| 38 | /* NSLU2 Timer */ | |
| 39 | #define NSLU2_FREQ 66000000 | |
| 40 | #define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) | |
| 41 | #define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC) | |
| 42 | ||
| 43 | /* GPIO */ | |
| 44 | ||
| 45 | #define NSLU2_GPIO0 0 | |
| 46 | #define NSLU2_GPIO1 1 | |
| 47 | #define NSLU2_GPIO2 2 | |
| 48 | #define NSLU2_GPIO3 3 | |
| 49 | #define NSLU2_GPIO4 4 | |
| 50 | #define NSLU2_GPIO5 5 | |
| 51 | #define NSLU2_GPIO6 6 | |
| 52 | #define NSLU2_GPIO7 7 | |
| 53 | #define NSLU2_GPIO8 8 | |
| 54 | #define NSLU2_GPIO9 9 | |
| 55 | #define NSLU2_GPIO10 10 | |
| 56 | #define NSLU2_GPIO11 11 | |
| 57 | #define NSLU2_GPIO12 12 | |
| 58 | #define NSLU2_GPIO13 13 | |
| 59 | #define NSLU2_GPIO14 14 | |
| 60 | #define NSLU2_GPIO15 15 | |
| 61 | ||
| 62 | /* Buttons */ | |
| 63 | ||
| 64 | #define NSLU2_PB_GPIO NSLU2_GPIO5 | |
| 65 | #define NSLU2_PO_GPIO NSLU2_GPIO8 /* power off */ | |
| 66 | #define NSLU2_RB_GPIO NSLU2_GPIO12 | |
| 67 | ||
| 68 | #define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5 | |
| 69 | #define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12 | |
| 70 | ||
| 71 | #define NSLU2_PB_BM (1L << NSLU2_PB_GPIO) | |
| 72 | #define NSLU2_PO_BM (1L << NSLU2_PO_GPIO) | |
| 73 | #define NSLU2_RB_BM (1L << NSLU2_RB_GPIO) | |
| 74 | ||
| 75 | /* Buzzer */ | |
| 76 | ||
| 77 | #define NSLU2_GPIO_BUZZ 4 | |
| 78 | #define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ) | |
| a47d08e2 | 79 | |
| a7918f39 AZ |
80 | /* LEDs */ |
| 81 | ||
| 82 | #define NSLU2_LED_RED NSLU2_GPIO0 | |
| 83 | #define NSLU2_LED_GRN NSLU2_GPIO1 | |
| 84 | ||
| 85 | #define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED) | |
| 86 | #define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN) | |
| 87 | ||
| a47d08e2 RW |
88 | #define NSLU2_LED_DISK1 NSLU2_GPIO3 |
| 89 | #define NSLU2_LED_DISK2 NSLU2_GPIO2 | |
| a7918f39 AZ |
90 | |
| 91 | #define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2) | |
| 92 | #define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3) | |
| 93 | ||
| 94 |