Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/arch-pxa/pxa-regs.h | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __PXA_REGS_H | |
14 | #define __PXA_REGS_H | |
15 | ||
1da177e4 LT |
16 | |
17 | /* | |
18 | * PXA Chip selects | |
19 | */ | |
20 | ||
21 | #define PXA_CS0_PHYS 0x00000000 | |
22 | #define PXA_CS1_PHYS 0x04000000 | |
23 | #define PXA_CS2_PHYS 0x08000000 | |
24 | #define PXA_CS3_PHYS 0x0C000000 | |
25 | #define PXA_CS4_PHYS 0x10000000 | |
26 | #define PXA_CS5_PHYS 0x14000000 | |
27 | ||
28 | ||
29 | /* | |
30 | * Personal Computer Memory Card International Association (PCMCIA) sockets | |
31 | */ | |
32 | ||
33 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | |
34 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | |
35 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | |
36 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | |
37 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | |
38 | ||
39 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | |
40 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | |
41 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | |
42 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | |
43 | ||
44 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | |
45 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | |
46 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | |
47 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | |
48 | ||
49 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | |
50 | (0x20000000 + (Nb)*PCMCIASp) | |
51 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ | |
52 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | |
53 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) | |
54 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | |
55 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) | |
56 | ||
57 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ | |
58 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ | |
59 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ | |
60 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ | |
61 | ||
62 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ | |
63 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ | |
64 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ | |
65 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ | |
66 | ||
67 | ||
68 | ||
69 | /* | |
70 | * DMA Controller | |
71 | */ | |
72 | ||
73 | #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ | |
74 | #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ | |
75 | #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ | |
76 | #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ | |
77 | #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ | |
78 | #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ | |
79 | #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ | |
80 | #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ | |
81 | #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ | |
82 | #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ | |
83 | #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ | |
84 | #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ | |
85 | #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ | |
86 | #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ | |
87 | #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ | |
88 | #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ | |
89 | ||
90 | #define DCSR(x) __REG2(0x40000000, (x) << 2) | |
91 | ||
92 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | |
93 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | |
94 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | |
95 | #ifdef CONFIG_PXA27x | |
96 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | |
97 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | |
98 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | |
99 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | |
100 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | |
101 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | |
102 | #define DCSR_ENRINTR (1 << 9) /* The end of Receive */ | |
103 | #endif | |
104 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | |
105 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | |
106 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | |
107 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | |
108 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | |
109 | ||
68477d11 | 110 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ |
1da177e4 LT |
111 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ |
112 | ||
113 | #define DRCMR(n) __REG2(0x40000100, (n)<<2) | |
114 | #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */ | |
115 | #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */ | |
116 | #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */ | |
117 | #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ | |
118 | #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */ | |
119 | #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ | |
120 | #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */ | |
121 | #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ | |
122 | #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ | |
123 | #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ | |
124 | #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ | |
125 | #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ | |
126 | #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ | |
127 | #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */ | |
128 | #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */ | |
a451e28c LG |
129 | #define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */ |
130 | #define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */ | |
1da177e4 LT |
131 | #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */ |
132 | #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */ | |
133 | #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */ | |
134 | #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */ | |
135 | #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */ | |
136 | #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */ | |
137 | #define DRCMR23 __REG(0x4000015c) /* Reserved */ | |
138 | #define DRCMR24 __REG(0x40000160) /* Reserved */ | |
139 | #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ | |
140 | #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ | |
141 | #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ | |
142 | #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ | |
143 | #define DRCMR29 __REG(0x40000174) /* Reserved */ | |
144 | #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ | |
145 | #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ | |
146 | #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ | |
147 | #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ | |
148 | #define DRCMR34 __REG(0x40000188) /* Reserved */ | |
149 | #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ | |
150 | #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ | |
151 | #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ | |
152 | #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ | |
153 | #define DRCMR39 __REG(0x4000019C) /* Reserved */ | |
a451e28c LG |
154 | #define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */ |
155 | #define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */ | |
1da177e4 LT |
156 | #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ |
157 | #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ | |
158 | #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ | |
159 | ||
160 | #define DRCMRRXSADR DRCMR2 | |
161 | #define DRCMRTXSADR DRCMR3 | |
162 | #define DRCMRRXBTRBR DRCMR4 | |
163 | #define DRCMRTXBTTHR DRCMR5 | |
164 | #define DRCMRRXFFRBR DRCMR6 | |
165 | #define DRCMRTXFFTHR DRCMR7 | |
166 | #define DRCMRRXMCDR DRCMR8 | |
167 | #define DRCMRRXMODR DRCMR9 | |
168 | #define DRCMRTXMODR DRCMR10 | |
169 | #define DRCMRRXPCDR DRCMR11 | |
170 | #define DRCMRTXPCDR DRCMR12 | |
171 | #define DRCMRRXSSDR DRCMR13 | |
172 | #define DRCMRTXSSDR DRCMR14 | |
173 | #define DRCMRRXSS2DR DRCMR15 | |
174 | #define DRCMRTXSS2DR DRCMR16 | |
175 | #define DRCMRRXICDR DRCMR17 | |
176 | #define DRCMRTXICDR DRCMR18 | |
177 | #define DRCMRRXSTRBR DRCMR19 | |
178 | #define DRCMRTXSTTHR DRCMR20 | |
179 | #define DRCMRRXMMC DRCMR21 | |
180 | #define DRCMRTXMMC DRCMR22 | |
181 | #define DRCMRRXSS3DR DRCMR66 | |
182 | #define DRCMRTXSS3DR DRCMR67 | |
183 | #define DRCMRUDC(x) DRCMR((x) + 24) | |
184 | ||
185 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ | |
186 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | |
187 | ||
188 | #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */ | |
189 | #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */ | |
190 | #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */ | |
191 | #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ | |
192 | #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */ | |
193 | #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */ | |
194 | #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */ | |
195 | #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ | |
196 | #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */ | |
197 | #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */ | |
198 | #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */ | |
199 | #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ | |
200 | #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */ | |
201 | #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */ | |
202 | #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */ | |
203 | #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ | |
204 | #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */ | |
205 | #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */ | |
206 | #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */ | |
207 | #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ | |
208 | #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */ | |
209 | #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */ | |
210 | #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */ | |
211 | #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ | |
212 | #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */ | |
213 | #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */ | |
214 | #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */ | |
215 | #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ | |
216 | #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */ | |
217 | #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */ | |
218 | #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */ | |
219 | #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ | |
220 | #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */ | |
221 | #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */ | |
222 | #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */ | |
223 | #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ | |
224 | #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */ | |
225 | #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */ | |
226 | #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */ | |
227 | #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ | |
228 | #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */ | |
229 | #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */ | |
230 | #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */ | |
231 | #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ | |
232 | #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */ | |
233 | #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */ | |
234 | #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */ | |
235 | #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ | |
236 | #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */ | |
237 | #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */ | |
238 | #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */ | |
239 | #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ | |
240 | #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */ | |
241 | #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */ | |
242 | #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */ | |
243 | #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ | |
244 | #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */ | |
245 | #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */ | |
246 | #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */ | |
247 | #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ | |
248 | #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */ | |
249 | #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */ | |
250 | #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */ | |
251 | #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ | |
252 | ||
253 | #define DDADR(x) __REG2(0x40000200, (x) << 4) | |
254 | #define DSADR(x) __REG2(0x40000204, (x) << 4) | |
255 | #define DTADR(x) __REG2(0x40000208, (x) << 4) | |
256 | #define DCMD(x) __REG2(0x4000020c, (x) << 4) | |
257 | ||
258 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | |
259 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | |
260 | ||
261 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | |
262 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | |
263 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | |
264 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | |
265 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | |
266 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | |
267 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | |
268 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | |
269 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | |
270 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | |
271 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | |
272 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | |
273 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | |
274 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | |
275 | ||
276 | ||
277 | /* | |
278 | * UARTs | |
279 | */ | |
280 | ||
281 | /* Full Function UART (FFUART) */ | |
282 | #define FFUART FFRBR | |
283 | #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ | |
284 | #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ | |
285 | #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ | |
286 | #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ | |
287 | #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ | |
288 | #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ | |
289 | #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ | |
290 | #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ | |
291 | #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ | |
292 | #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ | |
293 | #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ | |
294 | #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
295 | #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
296 | ||
297 | /* Bluetooth UART (BTUART) */ | |
298 | #define BTUART BTRBR | |
299 | #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ | |
300 | #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ | |
301 | #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ | |
302 | #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ | |
303 | #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ | |
304 | #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ | |
305 | #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ | |
306 | #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ | |
307 | #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ | |
308 | #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ | |
309 | #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ | |
310 | #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
311 | #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
312 | ||
313 | /* Standard UART (STUART) */ | |
314 | #define STUART STRBR | |
315 | #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ | |
316 | #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ | |
317 | #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ | |
318 | #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ | |
319 | #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ | |
320 | #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ | |
321 | #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ | |
322 | #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ | |
323 | #define STMSR __REG(0x40700018) /* Reserved */ | |
324 | #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ | |
325 | #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ | |
326 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
327 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
328 | ||
d9e29649 MR |
329 | /* Hardware UART (HWUART) */ |
330 | #define HWUART HWRBR | |
331 | #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ | |
332 | #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ | |
333 | #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ | |
334 | #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ | |
335 | #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ | |
336 | #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ | |
337 | #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ | |
338 | #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ | |
339 | #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ | |
340 | #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ | |
341 | #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ | |
342 | #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ | |
343 | #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ | |
344 | #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ | |
345 | #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
346 | #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
347 | ||
1da177e4 LT |
348 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ |
349 | #define IER_UUE (1 << 6) /* UART Unit Enable */ | |
350 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ | |
351 | #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ | |
352 | #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ | |
353 | #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ | |
354 | #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ | |
355 | #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ | |
356 | ||
357 | #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ | |
358 | #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ | |
359 | #define IIR_TOD (1 << 3) /* Time Out Detected */ | |
360 | #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ | |
361 | #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ | |
362 | #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ | |
363 | ||
364 | #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ | |
365 | #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ | |
366 | #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ | |
367 | #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ | |
368 | #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ | |
369 | #define FCR_ITL_1 (0) | |
370 | #define FCR_ITL_8 (FCR_ITL1) | |
371 | #define FCR_ITL_16 (FCR_ITL2) | |
372 | #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) | |
373 | ||
374 | #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ | |
375 | #define LCR_SB (1 << 6) /* Set Break */ | |
376 | #define LCR_STKYP (1 << 5) /* Sticky Parity */ | |
377 | #define LCR_EPS (1 << 4) /* Even Parity Select */ | |
378 | #define LCR_PEN (1 << 3) /* Parity Enable */ | |
379 | #define LCR_STB (1 << 2) /* Stop Bit */ | |
380 | #define LCR_WLS1 (1 << 1) /* Word Length Select */ | |
381 | #define LCR_WLS0 (1 << 0) /* Word Length Select */ | |
382 | ||
383 | #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ | |
384 | #define LSR_TEMT (1 << 6) /* Transmitter Empty */ | |
385 | #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ | |
386 | #define LSR_BI (1 << 4) /* Break Interrupt */ | |
387 | #define LSR_FE (1 << 3) /* Framing Error */ | |
388 | #define LSR_PE (1 << 2) /* Parity Error */ | |
389 | #define LSR_OE (1 << 1) /* Overrun Error */ | |
390 | #define LSR_DR (1 << 0) /* Data Ready */ | |
391 | ||
392 | #define MCR_LOOP (1 << 4) | |
393 | #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ | |
394 | #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ | |
395 | #define MCR_RTS (1 << 1) /* Request to Send */ | |
396 | #define MCR_DTR (1 << 0) /* Data Terminal Ready */ | |
397 | ||
398 | #define MSR_DCD (1 << 7) /* Data Carrier Detect */ | |
399 | #define MSR_RI (1 << 6) /* Ring Indicator */ | |
400 | #define MSR_DSR (1 << 5) /* Data Set Ready */ | |
401 | #define MSR_CTS (1 << 4) /* Clear To Send */ | |
402 | #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ | |
403 | #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ | |
404 | #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ | |
405 | #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ | |
406 | ||
407 | /* | |
408 | * IrSR (Infrared Selection Register) | |
409 | */ | |
410 | #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ | |
411 | #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ | |
412 | #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ | |
413 | #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ | |
414 | #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ | |
415 | ||
416 | ||
417 | /* | |
418 | * I2C registers | |
419 | */ | |
420 | ||
421 | #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */ | |
422 | #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */ | |
423 | #define ICR __REG(0x40301690) /* I2C Control Register - ICR */ | |
424 | #define ISR __REG(0x40301698) /* I2C Status Register - ISR */ | |
425 | #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ | |
426 | ||
427 | #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ | |
428 | #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */ | |
429 | #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */ | |
430 | #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */ | |
431 | #define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */ | |
432 | ||
433 | #define ICR_START (1 << 0) /* start bit */ | |
434 | #define ICR_STOP (1 << 1) /* stop bit */ | |
435 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ | |
436 | #define ICR_TB (1 << 3) /* transfer byte bit */ | |
437 | #define ICR_MA (1 << 4) /* master abort */ | |
438 | #define ICR_SCLE (1 << 5) /* master clock enable */ | |
439 | #define ICR_IUE (1 << 6) /* unit enable */ | |
440 | #define ICR_GCD (1 << 7) /* general call disable */ | |
441 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ | |
442 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ | |
443 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ | |
444 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ | |
445 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ | |
446 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ | |
447 | #define ICR_UR (1 << 14) /* unit reset */ | |
448 | ||
449 | #define ISR_RWM (1 << 0) /* read/write mode */ | |
450 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ | |
451 | #define ISR_UB (1 << 2) /* unit busy */ | |
452 | #define ISR_IBB (1 << 3) /* bus busy */ | |
453 | #define ISR_SSD (1 << 4) /* slave stop detected */ | |
454 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ | |
455 | #define ISR_ITE (1 << 6) /* tx buffer empty */ | |
456 | #define ISR_IRF (1 << 7) /* rx buffer full */ | |
457 | #define ISR_GCAD (1 << 8) /* general call address detected */ | |
458 | #define ISR_SAD (1 << 9) /* slave address detected */ | |
459 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ | |
460 | ||
461 | ||
462 | /* | |
463 | * Serial Audio Controller | |
464 | */ | |
465 | ||
466 | /* FIXME: This clash with SA1111 defines */ | |
467 | #ifndef _ASM_ARCH_SA1111 | |
468 | ||
469 | #define SACR0 __REG(0x40400000) /* Global Control Register */ | |
470 | #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ | |
471 | #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ | |
472 | #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ | |
473 | #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ | |
474 | #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ | |
475 | #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ | |
476 | ||
477 | #define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ | |
478 | #define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ | |
479 | #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ | |
480 | #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ | |
481 | #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ | |
482 | #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ | |
483 | #define SACR0_ENB (1 << 0) /* Enable I2S Link */ | |
484 | #define SACR1_ENLBF (1 << 5) /* Enable Loopback */ | |
485 | #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ | |
486 | #define SACR1_DREC (1 << 3) /* Disable Recording Function */ | |
fd88dd74 | 487 | #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ |
1da177e4 LT |
488 | |
489 | #define SASR0_I2SOFF (1 << 7) /* Controller Status */ | |
490 | #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ | |
491 | #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ | |
492 | #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ | |
493 | #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ | |
494 | #define SASR0_BSY (1 << 2) /* I2S Busy */ | |
495 | #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ | |
496 | #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ | |
497 | ||
498 | #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ | |
499 | #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ | |
500 | ||
501 | #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ | |
502 | #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ | |
503 | #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ | |
504 | #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ | |
505 | ||
506 | #endif | |
507 | ||
508 | /* | |
509 | * AC97 Controller registers | |
510 | */ | |
511 | ||
512 | #define POCR __REG(0x40500000) /* PCM Out Control Register */ | |
513 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | |
514 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
515 | ||
516 | #define PICR __REG(0x40500004) /* PCM In Control Register */ | |
517 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | |
518 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
519 | ||
520 | #define MCCR __REG(0x40500008) /* Mic In Control Register */ | |
521 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | |
522 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
523 | ||
524 | #define GCR __REG(0x4050000C) /* Global Control Register */ | |
525 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ | |
526 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ | |
527 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ | |
528 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ | |
529 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ | |
530 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ | |
531 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ | |
532 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ | |
533 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ | |
534 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ | |
535 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ | |
536 | ||
537 | #define POSR __REG(0x40500010) /* PCM Out Status Register */ | |
538 | #define POSR_FIFOE (1 << 4) /* FIFO error */ | |
539 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ | |
540 | ||
541 | #define PISR __REG(0x40500014) /* PCM In Status Register */ | |
542 | #define PISR_FIFOE (1 << 4) /* FIFO error */ | |
543 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | |
544 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ | |
545 | ||
546 | #define MCSR __REG(0x40500018) /* Mic In Status Register */ | |
547 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ | |
548 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | |
549 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ | |
550 | ||
551 | #define GSR __REG(0x4050001C) /* Global Status Register */ | |
552 | #define GSR_CDONE (1 << 19) /* Command Done */ | |
553 | #define GSR_SDONE (1 << 18) /* Status Done */ | |
554 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ | |
555 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ | |
556 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ | |
557 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ | |
558 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ | |
559 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ | |
560 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ | |
561 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ | |
562 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ | |
563 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ | |
564 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ | |
565 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ | |
566 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ | |
567 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ | |
568 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ | |
569 | ||
570 | #define CAR __REG(0x40500020) /* CODEC Access Register */ | |
571 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ | |
572 | ||
573 | #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ | |
574 | #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ | |
575 | ||
576 | #define MOCR __REG(0x40500100) /* Modem Out Control Register */ | |
577 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ | |
578 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
579 | ||
580 | #define MICR __REG(0x40500108) /* Modem In Control Register */ | |
581 | #define MICR_FEIE (1 << 3) /* FIFO Error */ | |
582 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
583 | ||
584 | #define MOSR __REG(0x40500110) /* Modem Out Status Register */ | |
585 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ | |
586 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ | |
587 | ||
588 | #define MISR __REG(0x40500118) /* Modem In Status Register */ | |
589 | #define MISR_FIFOE (1 << 4) /* FIFO error */ | |
590 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | |
591 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ | |
592 | ||
593 | #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ | |
594 | ||
595 | #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ | |
596 | #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ | |
597 | #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ | |
598 | #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ | |
599 | ||
600 | ||
601 | /* | |
602 | * USB Device Controller | |
603 | * PXA25x and PXA27x USB device controller registers are different. | |
604 | */ | |
605 | #if defined(CONFIG_PXA25x) | |
606 | ||
607 | #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ | |
608 | #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ | |
609 | #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ | |
610 | ||
611 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | |
612 | #define UDCCR_UDE (1 << 0) /* UDC enable */ | |
613 | #define UDCCR_UDA (1 << 1) /* UDC active */ | |
614 | #define UDCCR_RSM (1 << 2) /* Device resume */ | |
615 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | |
616 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | |
617 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | |
618 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | |
619 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | |
620 | ||
621 | #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ | |
622 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | |
623 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ | |
624 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | |
625 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | |
626 | #define UDCCS0_SST (1 << 4) /* Sent stall */ | |
627 | #define UDCCS0_FST (1 << 5) /* Force stall */ | |
628 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | |
629 | #define UDCCS0_SA (1 << 7) /* Setup active */ | |
630 | ||
631 | /* Bulk IN - Endpoint 1,6,11 */ | |
632 | #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ | |
633 | #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ | |
634 | #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ | |
635 | ||
636 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | |
637 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | |
638 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | |
639 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | |
640 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ | |
641 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ | |
642 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | |
643 | ||
644 | /* Bulk OUT - Endpoint 2,7,12 */ | |
645 | #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ | |
646 | #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ | |
647 | #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ | |
648 | ||
649 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | |
650 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | |
651 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ | |
652 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ | |
653 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ | |
654 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | |
655 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | |
656 | ||
657 | /* Isochronous IN - Endpoint 3,8,13 */ | |
658 | #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ | |
659 | #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ | |
660 | #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ | |
661 | ||
662 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | |
663 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | |
664 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | |
665 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | |
666 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | |
667 | ||
668 | /* Isochronous OUT - Endpoint 4,9,14 */ | |
669 | #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ | |
670 | #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ | |
671 | #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ | |
672 | ||
673 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | |
674 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | |
d1972efa | 675 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ |
1da177e4 LT |
676 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ |
677 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | |
678 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | |
679 | ||
680 | /* Interrupt IN - Endpoint 5,10,15 */ | |
681 | #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | |
682 | #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | |
683 | #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ | |
684 | ||
685 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | |
686 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | |
687 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | |
688 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | |
689 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ | |
690 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ | |
691 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | |
692 | ||
693 | #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ | |
694 | #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ | |
695 | #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ | |
696 | #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ | |
697 | #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ | |
698 | #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ | |
699 | #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ | |
700 | #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ | |
701 | #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ | |
702 | #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ | |
703 | #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ | |
704 | #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ | |
705 | #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ | |
706 | #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ | |
707 | #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ | |
708 | #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ | |
709 | #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ | |
710 | #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ | |
711 | #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ | |
712 | #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ | |
713 | #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ | |
714 | #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ | |
715 | #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ | |
716 | #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ | |
717 | ||
718 | #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ | |
719 | ||
720 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | |
721 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | |
722 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | |
723 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | |
724 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | |
725 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | |
726 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | |
727 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | |
728 | ||
729 | #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ | |
730 | ||
731 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | |
732 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | |
733 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | |
734 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | |
735 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | |
736 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | |
737 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | |
738 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | |
739 | ||
740 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ | |
741 | ||
742 | #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ | |
743 | #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ | |
744 | #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ | |
745 | #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ | |
746 | #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ | |
747 | #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ | |
748 | #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ | |
749 | #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ | |
750 | ||
751 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ | |
752 | ||
753 | #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ | |
754 | #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ | |
755 | #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ | |
756 | #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ | |
757 | #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ | |
758 | #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ | |
759 | #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ | |
760 | #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ | |
761 | ||
762 | #elif defined(CONFIG_PXA27x) | |
763 | ||
764 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | |
765 | #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ | |
766 | #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation | |
767 | Protocol Port Support */ | |
768 | #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol | |
769 | Support */ | |
770 | #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol | |
771 | Enable */ | |
772 | #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ | |
773 | #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ | |
774 | #define UDCCR_ACN_S 11 | |
775 | #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ | |
776 | #define UDCCR_AIN_S 8 | |
777 | #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface | |
778 | Setting Number */ | |
779 | #define UDCCR_AAISN_S 5 | |
780 | #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active | |
781 | Configuration */ | |
782 | #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration | |
783 | Error */ | |
784 | #define UDCCR_UDR (1 << 2) /* UDC Resume */ | |
785 | #define UDCCR_UDA (1 << 1) /* UDC Active */ | |
786 | #define UDCCR_UDE (1 << 0) /* UDC Enable */ | |
787 | ||
788 | #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ | |
789 | #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ | |
790 | #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ | |
791 | #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ | |
792 | ||
793 | #define UDC_INT_FIFOERROR (0x2) | |
794 | #define UDC_INT_PACKETCMP (0x1) | |
795 | ||
796 | #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | |
797 | #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ | |
798 | #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ | |
799 | #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ | |
800 | #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ | |
801 | #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ | |
802 | ||
803 | #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ | |
804 | #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ | |
805 | #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | |
806 | #define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */ | |
807 | #define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */ | |
808 | #define UDCISR1_IERU (1 << 29) /* IntEn - Resume */ | |
809 | #define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */ | |
810 | #define UDCISR1_IERS (1 << 27) /* IntEn - Reset */ | |
811 | ||
812 | ||
813 | #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ | |
814 | #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ | |
815 | #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ | |
816 | #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt | |
817 | Rising Edge Interrupt Enable */ | |
818 | #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt | |
819 | Falling Edge Interrupt Enable */ | |
820 | #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge | |
821 | Interrupt Enable */ | |
822 | #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge | |
823 | Interrupt Enable */ | |
824 | #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge | |
825 | Interrupt Enable */ | |
826 | #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge | |
827 | Interrupt Enable */ | |
828 | #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge | |
829 | Interrupt Enable */ | |
830 | #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge | |
831 | Interrupt Enable */ | |
832 | #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising | |
833 | Edge Interrupt Enable */ | |
834 | #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling | |
835 | Edge Interrupt Enable */ | |
836 | #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge | |
837 | Interrupt Enable */ | |
838 | #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge | |
839 | Interrupt Enable */ | |
840 | ||
3e88a579 RP |
841 | #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ |
842 | ||
843 | #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ | |
844 | #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ | |
845 | #define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ | |
846 | #define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ | |
847 | #define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ | |
848 | #define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ | |
849 | #define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ | |
850 | #define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ | |
851 | #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ | |
852 | #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ | |
853 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ | |
854 | #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ | |
855 | #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ | |
856 | #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ | |
857 | ||
1da177e4 LT |
858 | #define UDCCSN(x) __REG2(0x40600100, (x) << 2) |
859 | #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ | |
860 | #define UDCCSR0_SA (1 << 7) /* Setup Active */ | |
861 | #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ | |
862 | #define UDCCSR0_FST (1 << 5) /* Force Stall */ | |
863 | #define UDCCSR0_SST (1 << 4) /* Sent Stall */ | |
864 | #define UDCCSR0_DME (1 << 3) /* DMA Enable */ | |
865 | #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ | |
866 | #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ | |
867 | #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ | |
868 | ||
869 | #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ | |
870 | #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ | |
871 | #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ | |
872 | #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ | |
873 | #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ | |
874 | #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ | |
875 | #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ | |
876 | #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ | |
877 | #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ | |
878 | #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ | |
879 | #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ | |
880 | #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ | |
881 | #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ | |
882 | #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ | |
883 | #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ | |
884 | #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ | |
885 | #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ | |
886 | #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ | |
887 | #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ | |
888 | #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ | |
889 | #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ | |
890 | #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ | |
891 | #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ | |
892 | ||
893 | #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ | |
894 | #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ | |
895 | #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ | |
896 | #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ | |
897 | #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ | |
898 | #define UDCCSR_FST (1 << 5) /* Force STALL */ | |
899 | #define UDCCSR_SST (1 << 4) /* Sent STALL */ | |
900 | #define UDCCSR_DME (1 << 3) /* DMA Enable */ | |
901 | #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ | |
902 | #define UDCCSR_PC (1 << 1) /* Packet Complete */ | |
903 | #define UDCCSR_FS (1 << 0) /* FIFO needs service */ | |
904 | ||
905 | #define UDCBCN(x) __REG2(0x40600200, (x)<<2) | |
906 | #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ | |
907 | #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ | |
908 | #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ | |
909 | #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ | |
910 | #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ | |
911 | #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ | |
912 | #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ | |
913 | #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ | |
914 | #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ | |
915 | #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ | |
916 | #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ | |
917 | #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ | |
918 | #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ | |
919 | #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ | |
920 | #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ | |
921 | #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ | |
922 | #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ | |
923 | #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ | |
924 | #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ | |
925 | #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ | |
926 | #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ | |
927 | #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ | |
928 | #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ | |
929 | #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ | |
930 | ||
931 | #define UDCDN(x) __REG2(0x40600300, (x)<<2) | |
932 | #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) | |
933 | #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) | |
934 | #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ | |
935 | #define UDCDRA __REG(0x40600304) /* Data Register - EPA */ | |
936 | #define UDCDRB __REG(0x40600308) /* Data Register - EPB */ | |
937 | #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ | |
938 | #define UDCDRD __REG(0x40600310) /* Data Register - EPD */ | |
939 | #define UDCDRE __REG(0x40600314) /* Data Register - EPE */ | |
940 | #define UDCDRF __REG(0x40600318) /* Data Register - EPF */ | |
941 | #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ | |
942 | #define UDCDRH __REG(0x40600320) /* Data Register - EPH */ | |
943 | #define UDCDRI __REG(0x40600324) /* Data Register - EPI */ | |
944 | #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ | |
945 | #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ | |
946 | #define UDCDRL __REG(0x40600330) /* Data Register - EPL */ | |
947 | #define UDCDRM __REG(0x40600334) /* Data Register - EPM */ | |
948 | #define UDCDRN __REG(0x40600338) /* Data Register - EPN */ | |
949 | #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ | |
950 | #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ | |
951 | #define UDCDRR __REG(0x40600344) /* Data Register - EPR */ | |
952 | #define UDCDRS __REG(0x40600348) /* Data Register - EPS */ | |
953 | #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ | |
954 | #define UDCDRU __REG(0x40600350) /* Data Register - EPU */ | |
955 | #define UDCDRV __REG(0x40600354) /* Data Register - EPV */ | |
956 | #define UDCDRW __REG(0x40600358) /* Data Register - EPW */ | |
957 | #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ | |
958 | ||
959 | #define UDCCN(x) __REG2(0x40600400, (x)<<2) | |
960 | #define UDCCRA __REG(0x40600404) /* Configuration register EPA */ | |
961 | #define UDCCRB __REG(0x40600408) /* Configuration register EPB */ | |
962 | #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ | |
963 | #define UDCCRD __REG(0x40600410) /* Configuration register EPD */ | |
964 | #define UDCCRE __REG(0x40600414) /* Configuration register EPE */ | |
965 | #define UDCCRF __REG(0x40600418) /* Configuration register EPF */ | |
966 | #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ | |
967 | #define UDCCRH __REG(0x40600420) /* Configuration register EPH */ | |
968 | #define UDCCRI __REG(0x40600424) /* Configuration register EPI */ | |
969 | #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ | |
970 | #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ | |
971 | #define UDCCRL __REG(0x40600430) /* Configuration register EPL */ | |
972 | #define UDCCRM __REG(0x40600434) /* Configuration register EPM */ | |
973 | #define UDCCRN __REG(0x40600438) /* Configuration register EPN */ | |
974 | #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ | |
975 | #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ | |
976 | #define UDCCRR __REG(0x40600444) /* Configuration register EPR */ | |
977 | #define UDCCRS __REG(0x40600448) /* Configuration register EPS */ | |
978 | #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ | |
979 | #define UDCCRU __REG(0x40600450) /* Configuration register EPU */ | |
980 | #define UDCCRV __REG(0x40600454) /* Configuration register EPV */ | |
981 | #define UDCCRW __REG(0x40600458) /* Configuration register EPW */ | |
982 | #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ | |
983 | ||
984 | #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ | |
985 | #define UDCCONR_CN_S (25) | |
986 | #define UDCCONR_IN (0x07 << 22) /* Interface Number */ | |
987 | #define UDCCONR_IN_S (22) | |
988 | #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ | |
989 | #define UDCCONR_AISN_S (19) | |
990 | #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ | |
991 | #define UDCCONR_EN_S (15) | |
992 | #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ | |
993 | #define UDCCONR_ET_S (13) | |
994 | #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ | |
995 | #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ | |
996 | #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ | |
997 | #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ | |
998 | #define UDCCONR_ED (1 << 12) /* Endpoint Direction */ | |
999 | #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ | |
1000 | #define UDCCONR_MPS_S (2) | |
1001 | #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ | |
1002 | #define UDCCONR_EE (1 << 0) /* Endpoint Enable */ | |
1003 | ||
1004 | ||
1005 | #define UDC_INT_FIFOERROR (0x2) | |
1006 | #define UDC_INT_PACKETCMP (0x1) | |
1007 | ||
1008 | #define UDC_FNR_MASK (0x7ff) | |
1009 | ||
1010 | #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) | |
1011 | #define UDC_BCR_MASK (0x3ff) | |
1012 | #endif | |
1013 | ||
1014 | /* | |
1015 | * Fast Infrared Communication Port | |
1016 | */ | |
1017 | ||
1018 | #define FICP __REG(0x40800000) /* Start of FICP area */ | |
1019 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ | |
1020 | #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ | |
1021 | #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ | |
1022 | #define ICDR __REG(0x4080000c) /* ICP Data Register */ | |
1023 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ | |
1024 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ | |
1025 | ||
1026 | #define ICCR0_AME (1 << 7) /* Adress match enable */ | |
1027 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ | |
1028 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ | |
1029 | #define ICCR0_RXE (1 << 4) /* Receive enable */ | |
1030 | #define ICCR0_TXE (1 << 3) /* Transmit enable */ | |
1031 | #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ | |
1032 | #define ICCR0_LBM (1 << 1) /* Loopback mode */ | |
1033 | #define ICCR0_ITR (1 << 0) /* IrDA transmission */ | |
1034 | ||
1da177e4 LT |
1035 | #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ |
1036 | #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ | |
1037 | #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ | |
1038 | #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ | |
1039 | #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ | |
1040 | #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ | |
1da177e4 LT |
1041 | |
1042 | #ifdef CONFIG_PXA27x | |
1043 | #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ | |
1044 | #endif | |
1045 | #define ICSR0_FRE (1 << 5) /* Framing error */ | |
1046 | #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ | |
1047 | #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ | |
1048 | #define ICSR0_RAB (1 << 2) /* Receiver abort */ | |
1049 | #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ | |
1050 | #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ | |
1051 | ||
1052 | #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ | |
1053 | #define ICSR1_CRE (1 << 5) /* CRC error */ | |
1054 | #define ICSR1_EOF (1 << 4) /* End of frame */ | |
1055 | #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ | |
1056 | #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ | |
1057 | #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ | |
1058 | #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ | |
1059 | ||
1060 | ||
1061 | /* | |
1062 | * Real Time Clock | |
1063 | */ | |
1064 | ||
1065 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | |
1066 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | |
1067 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | |
1068 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | |
1069 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | |
1070 | ||
1071 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | |
1072 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | |
1073 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | |
1074 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | |
1075 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | |
1076 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | |
1077 | ||
1078 | ||
1079 | /* | |
1080 | * OS Timer & Match Registers | |
1081 | */ | |
1082 | ||
1083 | #define OSMR0 __REG(0x40A00000) /* */ | |
1084 | #define OSMR1 __REG(0x40A00004) /* */ | |
1085 | #define OSMR2 __REG(0x40A00008) /* */ | |
1086 | #define OSMR3 __REG(0x40A0000C) /* */ | |
1087 | #define OSMR4 __REG(0x40A00080) /* */ | |
1088 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | |
1089 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | |
1090 | #define OMCR4 __REG(0x40A000C0) /* */ | |
1091 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | |
1092 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | |
1093 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | |
1094 | ||
1095 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | |
1096 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | |
1097 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | |
1098 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | |
1099 | ||
1100 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | |
1101 | ||
1102 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | |
1103 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | |
1104 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | |
1105 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | |
1106 | ||
1107 | ||
1108 | /* | |
1109 | * Pulse Width Modulator | |
1110 | */ | |
1111 | ||
1112 | #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ | |
1113 | #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ | |
1114 | #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ | |
1115 | ||
1116 | #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ | |
1117 | #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ | |
1118 | #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ | |
1119 | ||
1120 | ||
1121 | /* | |
1122 | * Interrupt Controller | |
1123 | */ | |
1124 | ||
1125 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | |
1126 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | |
1127 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | |
1128 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | |
1129 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | |
1130 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | |
1131 | ||
1132 | ||
1133 | /* | |
1134 | * General Purpose I/O | |
1135 | */ | |
1136 | ||
1137 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ | |
1138 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ | |
1139 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ | |
1140 | ||
1141 | #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ | |
1142 | #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ | |
1143 | #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ | |
1144 | ||
1145 | #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ | |
1146 | #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ | |
1147 | #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ | |
1148 | ||
1149 | #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ | |
1150 | #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ | |
1151 | #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ | |
1152 | ||
1153 | #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ | |
1154 | #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ | |
1155 | #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ | |
1156 | ||
1157 | #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ | |
1158 | #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ | |
1159 | #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ | |
1160 | ||
1161 | #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ | |
1162 | #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ | |
1163 | #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ | |
1164 | ||
1165 | #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ | |
1166 | #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ | |
1167 | #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ | |
1168 | #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ | |
1169 | #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ | |
1170 | #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */ | |
1171 | #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ | |
1172 | #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ | |
1173 | ||
1174 | #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ | |
1175 | #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ | |
1176 | #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ | |
1177 | #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ | |
1178 | #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ | |
1179 | #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ | |
1180 | #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ | |
1181 | ||
1182 | /* More handy macros. The argument is a literal GPIO number. */ | |
1183 | ||
1184 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | |
1185 | ||
1186 | #ifdef CONFIG_PXA27x | |
1187 | ||
1188 | /* Interrupt Controller */ | |
1189 | ||
1190 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | |
1191 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | |
1192 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | |
1193 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | |
1194 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | |
1195 | ||
1196 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | |
1197 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | |
1198 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | |
1199 | #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | |
1200 | #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | |
1201 | #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | |
1202 | #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | |
1203 | #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | |
1204 | ||
1205 | #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) | |
1206 | #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) | |
1207 | #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) | |
1208 | #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) | |
1209 | #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) | |
1210 | #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) | |
1211 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) | |
1212 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ | |
1213 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) | |
1214 | #else | |
1215 | ||
1216 | #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | |
1217 | #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | |
1218 | #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | |
1219 | #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | |
1220 | #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | |
1221 | #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | |
1222 | #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | |
1223 | #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | |
1224 | ||
1225 | #endif | |
1226 | ||
1227 | ||
1228 | /* GPIO alternate function assignments */ | |
1229 | ||
1230 | #define GPIO1_RST 1 /* reset */ | |
1231 | #define GPIO6_MMCCLK 6 /* MMC Clock */ | |
1232 | #define GPIO7_48MHz 7 /* 48 MHz clock output */ | |
1233 | #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ | |
1234 | #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ | |
1235 | #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ | |
1236 | #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ | |
1237 | #define GPIO12_32KHz 12 /* 32 kHz out */ | |
1238 | #define GPIO13_MBGNT 13 /* memory controller grant */ | |
1239 | #define GPIO14_MBREQ 14 /* alternate bus master request */ | |
1240 | #define GPIO15_nCS_1 15 /* chip select 1 */ | |
1241 | #define GPIO16_PWM0 16 /* PWM0 output */ | |
1242 | #define GPIO17_PWM1 17 /* PWM1 output */ | |
1243 | #define GPIO18_RDY 18 /* Ext. Bus Ready */ | |
1244 | #define GPIO19_DREQ1 19 /* External DMA Request */ | |
1245 | #define GPIO20_DREQ0 20 /* External DMA Request */ | |
1246 | #define GPIO23_SCLK 23 /* SSP clock */ | |
1247 | #define GPIO24_SFRM 24 /* SSP Frame */ | |
1248 | #define GPIO25_STXD 25 /* SSP transmit */ | |
1249 | #define GPIO26_SRXD 26 /* SSP receive */ | |
1250 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ | |
1251 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ | |
1252 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ | |
1253 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ | |
1254 | #define GPIO31_SYNC 31 /* AC97/I2S sync */ | |
1255 | #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ | |
1256 | #define GPIO32_SYSCLK 32 /* I2S System Clock */ | |
1257 | #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ | |
1258 | #define GPIO33_nCS_5 33 /* chip select 5 */ | |
1259 | #define GPIO34_FFRXD 34 /* FFUART receive */ | |
1260 | #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ | |
1261 | #define GPIO35_FFCTS 35 /* FFUART Clear to send */ | |
1262 | #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ | |
1263 | #define GPIO37_FFDSR 37 /* FFUART data set ready */ | |
1264 | #define GPIO38_FFRI 38 /* FFUART Ring Indicator */ | |
1265 | #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ | |
1266 | #define GPIO39_FFTXD 39 /* FFUART transmit data */ | |
1267 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ | |
1268 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | |
1269 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | |
d9e29649 | 1270 | #define GPIO42_HWRXD 42 /* HWUART receive data */ |
1da177e4 | 1271 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ |
d9e29649 | 1272 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ |
1da177e4 | 1273 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ |
d9e29649 | 1274 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ |
1da177e4 | 1275 | #define GPIO45_BTRTS 45 /* BTUART request to send */ |
d9e29649 | 1276 | #define GPIO45_HWRTS 45 /* HWUART request to send */ |
1da177e4 LT |
1277 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ |
1278 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | |
1279 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | |
1280 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ | |
1281 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ | |
1282 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ | |
1283 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ | |
1284 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ | |
1285 | #define GPIO51_nPIOW 51 /* I/O Write for Card Space */ | |
1286 | #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ | |
1287 | #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ | |
1288 | #define GPIO53_MMCCLK 53 /* MMC Clock */ | |
1289 | #define GPIO54_MMCCLK 54 /* MMC Clock */ | |
1290 | #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ | |
1291 | #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ | |
1292 | #define GPIO55_nPREG 55 /* Card Address bit 26 */ | |
1293 | #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ | |
1294 | #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ | |
1295 | #define GPIO58_LDD_0 58 /* LCD data pin 0 */ | |
1296 | #define GPIO59_LDD_1 59 /* LCD data pin 1 */ | |
1297 | #define GPIO60_LDD_2 60 /* LCD data pin 2 */ | |
1298 | #define GPIO61_LDD_3 61 /* LCD data pin 3 */ | |
1299 | #define GPIO62_LDD_4 62 /* LCD data pin 4 */ | |
1300 | #define GPIO63_LDD_5 63 /* LCD data pin 5 */ | |
1301 | #define GPIO64_LDD_6 64 /* LCD data pin 6 */ | |
1302 | #define GPIO65_LDD_7 65 /* LCD data pin 7 */ | |
1303 | #define GPIO66_LDD_8 66 /* LCD data pin 8 */ | |
1304 | #define GPIO66_MBREQ 66 /* alternate bus master req */ | |
1305 | #define GPIO67_LDD_9 67 /* LCD data pin 9 */ | |
1306 | #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ | |
1307 | #define GPIO68_LDD_10 68 /* LCD data pin 10 */ | |
1308 | #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ | |
1309 | #define GPIO69_LDD_11 69 /* LCD data pin 11 */ | |
1310 | #define GPIO69_MMCCLK 69 /* MMC_CLK */ | |
1311 | #define GPIO70_LDD_12 70 /* LCD data pin 12 */ | |
1312 | #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ | |
1313 | #define GPIO71_LDD_13 71 /* LCD data pin 13 */ | |
1314 | #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ | |
1315 | #define GPIO72_LDD_14 72 /* LCD data pin 14 */ | |
1316 | #define GPIO72_32kHz 72 /* 32 kHz clock */ | |
1317 | #define GPIO73_LDD_15 73 /* LCD data pin 15 */ | |
1318 | #define GPIO73_MBGNT 73 /* Memory controller grant */ | |
1319 | #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ | |
1320 | #define GPIO75_LCD_LCLK 75 /* LCD line clock */ | |
1321 | #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ | |
1322 | #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ | |
1323 | #define GPIO78_nCS_2 78 /* chip select 2 */ | |
1324 | #define GPIO79_nCS_3 79 /* chip select 3 */ | |
1325 | #define GPIO80_nCS_4 80 /* chip select 4 */ | |
1326 | #define GPIO81_NSCLK 81 /* NSSP clock */ | |
1327 | #define GPIO82_NSFRM 82 /* NSSP Frame */ | |
1328 | #define GPIO83_NSTXD 83 /* NSSP transmit */ | |
1329 | #define GPIO84_NSRXD 84 /* NSSP receive */ | |
1330 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ | |
1331 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ |