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1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/io.h | |
3 | * | |
4 | * Copyright (C) 1996-2000 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Modifications: | |
11 | * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both | |
12 | * constant addresses and variable addresses. | |
13 | * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture | |
14 | * specific IO header files. | |
15 | * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. | |
16 | * 04-Apr-1999 PJB Added check_signature. | |
17 | * 12-Dec-1999 RMK More cleanups | |
18 | * 18-Jun-2000 RMK Removed virt_to_* and friends definitions | |
19 | * 05-Oct-2004 BJD Moved memory string functions to use void __iomem | |
20 | */ | |
21 | #ifndef __ASM_ARM_IO_H | |
22 | #define __ASM_ARM_IO_H | |
23 | ||
24 | #ifdef __KERNEL__ | |
25 | ||
26 | #include <linux/types.h> | |
27 | #include <asm/byteorder.h> | |
28 | #include <asm/memory.h> | |
1da177e4 LT |
29 | |
30 | /* | |
31 | * ISA I/O bus memory addresses are 1:1 with the physical address. | |
32 | */ | |
33 | #define isa_virt_to_bus virt_to_phys | |
34 | #define isa_page_to_bus page_to_phys | |
35 | #define isa_bus_to_virt phys_to_virt | |
36 | ||
37 | /* | |
38 | * Generic IO read/write. These perform native-endian accesses. Note | |
39 | * that some architectures will want to re-define __raw_{read,write}w. | |
40 | */ | |
41 | extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen); | |
42 | extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); | |
43 | extern void __raw_writesl(void __iomem *addr, const void *data, int longlen); | |
44 | ||
a0d95af5 DS |
45 | extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); |
46 | extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); | |
47 | extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); | |
1da177e4 LT |
48 | |
49 | #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v)) | |
50 | #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)) | |
51 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v)) | |
52 | ||
53 | #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a)) | |
54 | #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) | |
55 | #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) | |
56 | ||
67a1901f RK |
57 | /* |
58 | * Architecture ioremap implementation. | |
9d4ae727 DS |
59 | * |
60 | * __ioremap takes CPU physical address. | |
61 | * | |
62 | * __ioremap_pfn takes a Page Frame Number and an offset into that page | |
67a1901f | 63 | */ |
9d4ae727 | 64 | extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long); |
67a1901f | 65 | extern void __iomem * __ioremap(unsigned long, size_t, unsigned long); |
1622605c | 66 | extern void __iounmap(volatile void __iomem *addr); |
67a1901f | 67 | |
1da177e4 LT |
68 | /* |
69 | * Bad read/write accesses... | |
70 | */ | |
71 | extern void __readwrite_bug(const char *fn); | |
72 | ||
73 | /* | |
74 | * Now, pick up the machine-defined IO definitions | |
75 | */ | |
76 | #include <asm/arch/io.h> | |
77 | ||
78 | #ifdef __io_pci | |
79 | #warning machine class uses buggy __io_pci | |
80 | #endif | |
81 | #if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \ | |
82 | defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl) | |
83 | #warning machine class uses old __arch_putw or __arch_getw | |
84 | #endif | |
85 | ||
86 | /* | |
87 | * IO port access primitives | |
88 | * ------------------------- | |
89 | * | |
90 | * The ARM doesn't have special IO access instructions; all IO is memory | |
91 | * mapped. Note that these are defined to perform little endian accesses | |
92 | * only. Their primary purpose is to access PCI and ISA peripherals. | |
93 | * | |
94 | * Note that for a big endian machine, this implies that the following | |
c79ebfa8 | 95 | * big endian mode connectivity is in place, as described by numerous |
1da177e4 LT |
96 | * ARM documents: |
97 | * | |
98 | * PCI: D0-D7 D8-D15 D16-D23 D24-D31 | |
99 | * ARM: D24-D31 D16-D23 D8-D15 D0-D7 | |
100 | * | |
101 | * The machine specific io.h include defines __io to translate an "IO" | |
102 | * address to a memory address. | |
103 | * | |
104 | * Note that we prevent GCC re-ordering or caching values in expressions | |
105 | * by introducing sequence points into the in*() definitions. Note that | |
106 | * __raw_* do not guarantee this behaviour. | |
107 | * | |
108 | * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. | |
109 | */ | |
110 | #ifdef __io | |
111 | #define outb(v,p) __raw_writeb(v,__io(p)) | |
05f9869b OK |
112 | #define outw(v,p) __raw_writew((__force __u16) \ |
113 | cpu_to_le16(v),__io(p)) | |
114 | #define outl(v,p) __raw_writel((__force __u32) \ | |
115 | cpu_to_le32(v),__io(p)) | |
1da177e4 | 116 | |
05f9869b OK |
117 | #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; }) |
118 | #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ | |
119 | __raw_readw(__io(p))); __v; }) | |
120 | #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ | |
121 | __raw_readl(__io(p))); __v; }) | |
1da177e4 LT |
122 | |
123 | #define outsb(p,d,l) __raw_writesb(__io(p),d,l) | |
124 | #define outsw(p,d,l) __raw_writesw(__io(p),d,l) | |
125 | #define outsl(p,d,l) __raw_writesl(__io(p),d,l) | |
126 | ||
127 | #define insb(p,d,l) __raw_readsb(__io(p),d,l) | |
128 | #define insw(p,d,l) __raw_readsw(__io(p),d,l) | |
129 | #define insl(p,d,l) __raw_readsl(__io(p),d,l) | |
130 | #endif | |
131 | ||
132 | #define outb_p(val,port) outb((val),(port)) | |
133 | #define outw_p(val,port) outw((val),(port)) | |
134 | #define outl_p(val,port) outl((val),(port)) | |
135 | #define inb_p(port) inb((port)) | |
136 | #define inw_p(port) inw((port)) | |
137 | #define inl_p(port) inl((port)) | |
138 | ||
139 | #define outsb_p(port,from,len) outsb(port,from,len) | |
140 | #define outsw_p(port,from,len) outsw(port,from,len) | |
141 | #define outsl_p(port,from,len) outsl(port,from,len) | |
142 | #define insb_p(port,to,len) insb(port,to,len) | |
143 | #define insw_p(port,to,len) insw(port,to,len) | |
144 | #define insl_p(port,to,len) insl(port,to,len) | |
145 | ||
146 | /* | |
147 | * String version of IO memory access ops: | |
148 | */ | |
d2f60748 RK |
149 | extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); |
150 | extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); | |
151 | extern void _memset_io(volatile void __iomem *, int, size_t); | |
1da177e4 LT |
152 | |
153 | #define mmiowb() | |
154 | ||
155 | /* | |
156 | * Memory access primitives | |
157 | * ------------------------ | |
158 | * | |
159 | * These perform PCI memory accesses via an ioremap region. They don't | |
160 | * take an address as such, but a cookie. | |
161 | * | |
162 | * Again, this are defined to perform little endian accesses. See the | |
163 | * IO port primitives for more information. | |
164 | */ | |
165 | #ifdef __mem_pci | |
05f9869b OK |
166 | #define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; }) |
167 | #define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \ | |
168 | __raw_readw(__mem_pci(c))); __v; }) | |
169 | #define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \ | |
170 | __raw_readl(__mem_pci(c))); __v; }) | |
1da177e4 LT |
171 | #define readb_relaxed(addr) readb(addr) |
172 | #define readw_relaxed(addr) readw(addr) | |
173 | #define readl_relaxed(addr) readl(addr) | |
174 | ||
175 | #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l) | |
176 | #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l) | |
177 | #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) | |
178 | ||
179 | #define writeb(v,c) __raw_writeb(v,__mem_pci(c)) | |
05f9869b OK |
180 | #define writew(v,c) __raw_writew((__force __u16) \ |
181 | cpu_to_le16(v),__mem_pci(c)) | |
182 | #define writel(v,c) __raw_writel((__force __u32) \ | |
183 | cpu_to_le32(v),__mem_pci(c)) | |
1da177e4 LT |
184 | |
185 | #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l) | |
186 | #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l) | |
187 | #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l) | |
188 | ||
189 | #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) | |
190 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) | |
191 | #define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) | |
192 | ||
193 | #define eth_io_copy_and_sum(s,c,l,b) \ | |
194 | eth_copy_and_sum((s),__mem_pci(c),(l),(b)) | |
195 | ||
1da177e4 LT |
196 | #elif !defined(readb) |
197 | ||
198 | #define readb(c) (__readwrite_bug("readb"),0) | |
199 | #define readw(c) (__readwrite_bug("readw"),0) | |
200 | #define readl(c) (__readwrite_bug("readl"),0) | |
201 | #define writeb(v,c) __readwrite_bug("writeb") | |
202 | #define writew(v,c) __readwrite_bug("writew") | |
203 | #define writel(v,c) __readwrite_bug("writel") | |
204 | ||
205 | #define eth_io_copy_and_sum(s,c,l,b) __readwrite_bug("eth_io_copy_and_sum") | |
206 | ||
207 | #define check_signature(io,sig,len) (0) | |
208 | ||
209 | #endif /* __mem_pci */ | |
210 | ||
1da177e4 LT |
211 | /* |
212 | * ioremap and friends. | |
213 | * | |
214 | * ioremap takes a PCI memory address, as specified in | |
215 | * Documentation/IO-mapping.txt. | |
9d4ae727 | 216 | * |
1da177e4 | 217 | */ |
1da177e4 | 218 | #ifndef __arch_ioremap |
67a1901f RK |
219 | #define ioremap(cookie,size) __ioremap(cookie,size,0) |
220 | #define ioremap_nocache(cookie,size) __ioremap(cookie,size,0) | |
221 | #define ioremap_cached(cookie,size) __ioremap(cookie,size,L_PTE_CACHEABLE) | |
1da177e4 LT |
222 | #define iounmap(cookie) __iounmap(cookie) |
223 | #else | |
67a1901f RK |
224 | #define ioremap(cookie,size) __arch_ioremap((cookie),(size),0) |
225 | #define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0) | |
226 | #define ioremap_cached(cookie,size) __arch_ioremap((cookie),(size),L_PTE_CACHEABLE) | |
1da177e4 LT |
227 | #define iounmap(cookie) __arch_iounmap(cookie) |
228 | #endif | |
229 | ||
09f0551d RK |
230 | /* |
231 | * io{read,write}{8,16,32} macros | |
232 | */ | |
7533fca8 | 233 | #ifndef ioread8 |
09f0551d RK |
234 | #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) |
235 | #define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; }) | |
236 | #define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; }) | |
237 | ||
238 | #define iowrite8(v,p) __raw_writeb(v, p) | |
239 | #define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p) | |
240 | #define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p) | |
241 | ||
242 | #define ioread8_rep(p,d,c) __raw_readsb(p,d,c) | |
243 | #define ioread16_rep(p,d,c) __raw_readsw(p,d,c) | |
244 | #define ioread32_rep(p,d,c) __raw_readsl(p,d,c) | |
245 | ||
246 | #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c) | |
247 | #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c) | |
248 | #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c) | |
249 | ||
250 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | |
251 | extern void ioport_unmap(void __iomem *addr); | |
7533fca8 | 252 | #endif |
09f0551d RK |
253 | |
254 | struct pci_dev; | |
255 | ||
256 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); | |
257 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); | |
258 | ||
1da177e4 LT |
259 | /* |
260 | * can the hardware map this into one segment or not, given no other | |
261 | * constraints. | |
262 | */ | |
263 | #define BIOVEC_MERGEABLE(vec1, vec2) \ | |
264 | ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) | |
265 | ||
51635ad2 LB |
266 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE |
267 | extern int valid_phys_addr_range(unsigned long addr, size_t size); | |
268 | extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); | |
269 | ||
1da177e4 LT |
270 | /* |
271 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
272 | * access | |
273 | */ | |
274 | #define xlate_dev_mem_ptr(p) __va(p) | |
275 | ||
276 | /* | |
277 | * Convert a virtual cached pointer to an uncached pointer | |
278 | */ | |
279 | #define xlate_dev_kmem_ptr(p) p | |
280 | ||
1645f20b RK |
281 | /* |
282 | * Register ISA memory and port locations for glibc iopl/inb/outb | |
283 | * emulation. | |
284 | */ | |
285 | extern void register_isa_ports(unsigned int mmio, unsigned int io, | |
286 | unsigned int io_shift); | |
287 | ||
1da177e4 LT |
288 | #endif /* __KERNEL__ */ |
289 | #endif /* __ASM_ARM_IO_H */ |