Commit | Line | Data |
---|---|---|
19381f02 BW |
1 | /* |
2 | * File: include/asm-blackfin/mach-bf527/defBF525.h | |
3 | * Based on: | |
4 | * Author: | |
5 | * | |
6 | * Created: | |
7 | * Description: | |
8 | * | |
9 | * Rev: | |
10 | * | |
11 | * Modified: | |
12 | * | |
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2, or (at your option) | |
18 | * any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; see the file COPYING. | |
27 | * If not, write to the Free Software Foundation, | |
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
29 | */ | |
30 | ||
31 | #ifndef _DEF_BF525_H | |
32 | #define _DEF_BF525_H | |
33 | ||
34 | /* Include all Core registers and bit definitions */ | |
35 | #include <asm/mach-common/def_LPBlackfin.h> | |
36 | ||
37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ | |
38 | ||
39 | /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | |
40 | #include "defBF52x_base.h" | |
41 | ||
42 | /* The following are the #defines needed by ADSP-BF525 that are not in the common header */ | |
43 | ||
44 | /* USB Control Registers */ | |
45 | ||
46 | #define USB_FADDR 0xffc03800 /* Function address register */ | |
47 | #define USB_POWER 0xffc03804 /* Power management register */ | |
48 | #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ | |
49 | #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ | |
50 | #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ | |
51 | #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ | |
52 | #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ | |
53 | #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ | |
54 | #define USB_FRAME 0xffc03820 /* USB frame number */ | |
55 | #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ | |
56 | #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ | |
57 | #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ | |
58 | #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ | |
59 | ||
60 | /* USB Packet Control Registers */ | |
61 | ||
62 | #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ | |
63 | #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | |
64 | #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | |
65 | #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ | |
66 | #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ | |
67 | #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | |
68 | #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | |
69 | #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ | |
70 | #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | |
71 | #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | |
72 | #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ | |
73 | #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ | |
74 | #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ | |
75 | ||
76 | /* USB Endpoint FIFO Registers */ | |
77 | ||
78 | #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ | |
79 | #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ | |
80 | #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ | |
81 | #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ | |
82 | #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ | |
83 | #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ | |
84 | #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ | |
85 | #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ | |
86 | ||
87 | /* USB OTG Control Registers */ | |
88 | ||
89 | #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ | |
90 | #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ | |
91 | #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ | |
92 | ||
93 | /* USB Phy Control Registers */ | |
94 | ||
95 | #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ | |
96 | #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ | |
97 | #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ | |
98 | #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ | |
99 | #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ | |
100 | ||
101 | /* (APHY_CNTRL is for ADI usage only) */ | |
102 | ||
103 | #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ | |
104 | ||
105 | /* (APHY_CALIB is for ADI usage only) */ | |
106 | ||
107 | #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ | |
108 | ||
109 | #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ | |
110 | ||
111 | /* (PHY_TEST is for ADI usage only) */ | |
112 | ||
113 | #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ | |
114 | ||
115 | #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ | |
116 | #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ | |
117 | ||
118 | /* USB Endpoint 0 Control Registers */ | |
119 | ||
120 | #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ | |
121 | #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ | |
122 | #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ | |
123 | #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ | |
124 | #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ | |
125 | #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ | |
126 | #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ | |
127 | #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ | |
128 | #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ | |
129 | #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ | |
130 | ||
131 | /* USB Endpoint 1 Control Registers */ | |
132 | ||
133 | #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ | |
134 | #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ | |
135 | #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ | |
136 | #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ | |
137 | #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ | |
138 | #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ | |
139 | #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ | |
140 | #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ | |
141 | #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ | |
142 | #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ | |
143 | ||
144 | /* USB Endpoint 2 Control Registers */ | |
145 | ||
146 | #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ | |
147 | #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ | |
148 | #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ | |
149 | #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ | |
150 | #define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ | |
151 | #define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ | |
152 | #define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ | |
153 | #define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ | |
154 | #define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ | |
155 | #define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ | |
156 | ||
157 | /* USB Endpoint 3 Control Registers */ | |
158 | ||
159 | #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ | |
160 | #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ | |
161 | #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ | |
162 | #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ | |
163 | #define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ | |
164 | #define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ | |
165 | #define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ | |
166 | #define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ | |
167 | #define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ | |
168 | #define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ | |
169 | ||
170 | /* USB Endpoint 4 Control Registers */ | |
171 | ||
172 | #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ | |
173 | #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ | |
174 | #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ | |
175 | #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ | |
176 | #define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ | |
177 | #define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ | |
178 | #define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ | |
179 | #define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ | |
180 | #define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ | |
181 | #define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ | |
182 | ||
183 | /* USB Endpoint 5 Control Registers */ | |
184 | ||
185 | #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ | |
186 | #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ | |
187 | #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ | |
188 | #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ | |
189 | #define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ | |
190 | #define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ | |
191 | #define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ | |
192 | #define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ | |
193 | #define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ | |
194 | #define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ | |
195 | ||
196 | /* USB Endpoint 6 Control Registers */ | |
197 | ||
198 | #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ | |
199 | #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ | |
200 | #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ | |
201 | #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ | |
202 | #define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ | |
203 | #define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ | |
204 | #define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ | |
205 | #define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ | |
206 | #define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ | |
207 | #define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ | |
208 | ||
209 | /* USB Endpoint 7 Control Registers */ | |
210 | ||
211 | #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ | |
212 | #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ | |
213 | #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ | |
214 | #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ | |
215 | #define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ | |
216 | #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ | |
217 | #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ | |
218 | #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ | |
219 | #define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ | |
220 | #define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ | |
221 | ||
222 | #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ | |
223 | ||
224 | /* USB Channel 0 Config Registers */ | |
225 | ||
226 | #define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ | |
227 | #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ | |
228 | #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ | |
229 | #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ | |
230 | #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ | |
231 | ||
232 | /* USB Channel 1 Config Registers */ | |
233 | ||
234 | #define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ | |
235 | #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ | |
236 | #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ | |
237 | #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ | |
238 | #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ | |
239 | ||
240 | /* USB Channel 2 Config Registers */ | |
241 | ||
242 | #define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ | |
243 | #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ | |
244 | #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ | |
245 | #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ | |
246 | #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ | |
247 | ||
248 | /* USB Channel 3 Config Registers */ | |
249 | ||
250 | #define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ | |
251 | #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ | |
252 | #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ | |
253 | #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ | |
254 | #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ | |
255 | ||
256 | /* USB Channel 4 Config Registers */ | |
257 | ||
258 | #define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ | |
259 | #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ | |
260 | #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ | |
261 | #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ | |
262 | #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ | |
263 | ||
264 | /* USB Channel 5 Config Registers */ | |
265 | ||
266 | #define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ | |
267 | #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ | |
268 | #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ | |
269 | #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ | |
270 | #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ | |
271 | ||
272 | /* USB Channel 6 Config Registers */ | |
273 | ||
274 | #define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ | |
275 | #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ | |
276 | #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ | |
277 | #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ | |
278 | #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ | |
279 | ||
280 | /* USB Channel 7 Config Registers */ | |
281 | ||
282 | #define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ | |
283 | #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ | |
284 | #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ | |
285 | #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ | |
286 | #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ | |
287 | ||
288 | /* Bit masks for USB_FADDR */ | |
289 | ||
290 | #define FUNCTION_ADDRESS 0x7f /* Function address */ | |
291 | ||
292 | /* Bit masks for USB_POWER */ | |
293 | ||
294 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | |
295 | #define nENABLE_SUSPENDM 0x0 | |
296 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | |
297 | #define nSUSPEND_MODE 0x0 | |
298 | #define RESUME_MODE 0x4 /* DMA Mode */ | |
299 | #define nRESUME_MODE 0x0 | |
300 | #define RESET 0x8 /* Reset indicator */ | |
301 | #define nRESET 0x0 | |
302 | #define HS_MODE 0x10 /* High Speed mode indicator */ | |
303 | #define nHS_MODE 0x0 | |
304 | #define HS_ENABLE 0x20 /* high Speed Enable */ | |
305 | #define nHS_ENABLE 0x0 | |
306 | #define SOFT_CONN 0x40 /* Soft connect */ | |
307 | #define nSOFT_CONN 0x0 | |
308 | #define ISO_UPDATE 0x80 /* Isochronous update */ | |
309 | #define nISO_UPDATE 0x0 | |
310 | ||
311 | /* Bit masks for USB_INTRTX */ | |
312 | ||
313 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | |
314 | #define nEP0_TX 0x0 | |
315 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | |
316 | #define nEP1_TX 0x0 | |
317 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | |
318 | #define nEP2_TX 0x0 | |
319 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | |
320 | #define nEP3_TX 0x0 | |
321 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | |
322 | #define nEP4_TX 0x0 | |
323 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | |
324 | #define nEP5_TX 0x0 | |
325 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | |
326 | #define nEP6_TX 0x0 | |
327 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | |
328 | #define nEP7_TX 0x0 | |
329 | ||
330 | /* Bit masks for USB_INTRRX */ | |
331 | ||
332 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | |
333 | #define nEP1_RX 0x0 | |
334 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | |
335 | #define nEP2_RX 0x0 | |
336 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | |
337 | #define nEP3_RX 0x0 | |
338 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | |
339 | #define nEP4_RX 0x0 | |
340 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | |
341 | #define nEP5_RX 0x0 | |
342 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | |
343 | #define nEP6_RX 0x0 | |
344 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | |
345 | #define nEP7_RX 0x0 | |
346 | ||
347 | /* Bit masks for USB_INTRTXE */ | |
348 | ||
349 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | |
350 | #define nEP0_TX_E 0x0 | |
351 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | |
352 | #define nEP1_TX_E 0x0 | |
353 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | |
354 | #define nEP2_TX_E 0x0 | |
355 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | |
356 | #define nEP3_TX_E 0x0 | |
357 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | |
358 | #define nEP4_TX_E 0x0 | |
359 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | |
360 | #define nEP5_TX_E 0x0 | |
361 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | |
362 | #define nEP6_TX_E 0x0 | |
363 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | |
364 | #define nEP7_TX_E 0x0 | |
365 | ||
366 | /* Bit masks for USB_INTRRXE */ | |
367 | ||
368 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | |
369 | #define nEP1_RX_E 0x0 | |
370 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | |
371 | #define nEP2_RX_E 0x0 | |
372 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | |
373 | #define nEP3_RX_E 0x0 | |
374 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | |
375 | #define nEP4_RX_E 0x0 | |
376 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | |
377 | #define nEP5_RX_E 0x0 | |
378 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | |
379 | #define nEP6_RX_E 0x0 | |
380 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | |
381 | #define nEP7_RX_E 0x0 | |
382 | ||
383 | /* Bit masks for USB_INTRUSB */ | |
384 | ||
385 | #define SUSPEND_B 0x1 /* Suspend indicator */ | |
386 | #define nSUSPEND_B 0x0 | |
387 | #define RESUME_B 0x2 /* Resume indicator */ | |
388 | #define nRESUME_B 0x0 | |
389 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | |
390 | #define nRESET_OR_BABLE_B 0x0 | |
391 | #define SOF_B 0x8 /* Start of frame */ | |
392 | #define nSOF_B 0x0 | |
393 | #define CONN_B 0x10 /* Connection indicator */ | |
394 | #define nCONN_B 0x0 | |
395 | #define DISCON_B 0x20 /* Disconnect indicator */ | |
396 | #define nDISCON_B 0x0 | |
397 | #define SESSION_REQ_B 0x40 /* Session Request */ | |
398 | #define nSESSION_REQ_B 0x0 | |
399 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | |
400 | #define nVBUS_ERROR_B 0x0 | |
401 | ||
402 | /* Bit masks for USB_INTRUSBE */ | |
403 | ||
404 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | |
405 | #define nSUSPEND_BE 0x0 | |
406 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | |
407 | #define nRESUME_BE 0x0 | |
408 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | |
409 | #define nRESET_OR_BABLE_BE 0x0 | |
410 | #define SOF_BE 0x8 /* Start of frame int enable */ | |
411 | #define nSOF_BE 0x0 | |
412 | #define CONN_BE 0x10 /* Connection indicator int enable */ | |
413 | #define nCONN_BE 0x0 | |
414 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | |
415 | #define nDISCON_BE 0x0 | |
416 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | |
417 | #define nSESSION_REQ_BE 0x0 | |
418 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | |
419 | #define nVBUS_ERROR_BE 0x0 | |
420 | ||
421 | /* Bit masks for USB_FRAME */ | |
422 | ||
423 | #define FRAME_NUMBER 0x7ff /* Frame number */ | |
424 | ||
425 | /* Bit masks for USB_INDEX */ | |
426 | ||
427 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ | |
428 | ||
429 | /* Bit masks for USB_GLOBAL_CTL */ | |
430 | ||
431 | #define GLOBAL_ENA 0x1 /* enables USB module */ | |
432 | #define nGLOBAL_ENA 0x0 | |
433 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | |
434 | #define nEP1_TX_ENA 0x0 | |
435 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | |
436 | #define nEP2_TX_ENA 0x0 | |
437 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | |
438 | #define nEP3_TX_ENA 0x0 | |
439 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | |
440 | #define nEP4_TX_ENA 0x0 | |
441 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | |
442 | #define nEP5_TX_ENA 0x0 | |
443 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | |
444 | #define nEP6_TX_ENA 0x0 | |
445 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | |
446 | #define nEP7_TX_ENA 0x0 | |
447 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | |
448 | #define nEP1_RX_ENA 0x0 | |
449 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | |
450 | #define nEP2_RX_ENA 0x0 | |
451 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | |
452 | #define nEP3_RX_ENA 0x0 | |
453 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | |
454 | #define nEP4_RX_ENA 0x0 | |
455 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | |
456 | #define nEP5_RX_ENA 0x0 | |
457 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | |
458 | #define nEP6_RX_ENA 0x0 | |
459 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | |
460 | #define nEP7_RX_ENA 0x0 | |
461 | ||
462 | /* Bit masks for USB_OTG_DEV_CTL */ | |
463 | ||
464 | #define SESSION 0x1 /* session indicator */ | |
465 | #define nSESSION 0x0 | |
466 | #define HOST_REQ 0x2 /* Host negotiation request */ | |
467 | #define nHOST_REQ 0x0 | |
468 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | |
469 | #define nHOST_MODE 0x0 | |
470 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | |
471 | #define nVBUS0 0x0 | |
472 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | |
473 | #define nVBUS1 0x0 | |
474 | #define LSDEV 0x20 /* Low-speed indicator */ | |
475 | #define nLSDEV 0x0 | |
476 | #define FSDEV 0x40 /* Full or High-speed indicator */ | |
477 | #define nFSDEV 0x0 | |
478 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | |
479 | #define nB_DEVICE 0x0 | |
480 | ||
481 | /* Bit masks for USB_OTG_VBUS_IRQ */ | |
482 | ||
483 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | |
484 | #define nDRIVE_VBUS_ON 0x0 | |
485 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | |
486 | #define nDRIVE_VBUS_OFF 0x0 | |
487 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | |
488 | #define nCHRG_VBUS_START 0x0 | |
489 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | |
490 | #define nCHRG_VBUS_END 0x0 | |
491 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | |
492 | #define nDISCHRG_VBUS_START 0x0 | |
493 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | |
494 | #define nDISCHRG_VBUS_END 0x0 | |
495 | ||
496 | /* Bit masks for USB_OTG_VBUS_MASK */ | |
497 | ||
498 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | |
499 | #define nDRIVE_VBUS_ON_ENA 0x0 | |
500 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | |
501 | #define nDRIVE_VBUS_OFF_ENA 0x0 | |
502 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | |
503 | #define nCHRG_VBUS_START_ENA 0x0 | |
504 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | |
505 | #define nCHRG_VBUS_END_ENA 0x0 | |
506 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | |
507 | #define nDISCHRG_VBUS_START_ENA 0x0 | |
508 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | |
509 | #define nDISCHRG_VBUS_END_ENA 0x0 | |
510 | ||
511 | /* Bit masks for USB_CSR0 */ | |
512 | ||
513 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | |
514 | #define nRXPKTRDY 0x0 | |
515 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | |
516 | #define nTXPKTRDY 0x0 | |
517 | #define STALL_SENT 0x4 /* STALL handshake sent */ | |
518 | #define nSTALL_SENT 0x0 | |
519 | #define DATAEND 0x8 /* Data end indicator */ | |
520 | #define nDATAEND 0x0 | |
521 | #define SETUPEND 0x10 /* Setup end */ | |
522 | #define nSETUPEND 0x0 | |
523 | #define SENDSTALL 0x20 /* Send STALL handshake */ | |
524 | #define nSENDSTALL 0x0 | |
525 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | |
526 | #define nSERVICED_RXPKTRDY 0x0 | |
527 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | |
528 | #define nSERVICED_SETUPEND 0x0 | |
529 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | |
530 | #define nFLUSHFIFO 0x0 | |
531 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | |
532 | #define nSTALL_RECEIVED_H 0x0 | |
533 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | |
534 | #define nSETUPPKT_H 0x0 | |
535 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | |
536 | #define nERROR_H 0x0 | |
537 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | |
538 | #define nREQPKT_H 0x0 | |
539 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | |
540 | #define nSTATUSPKT_H 0x0 | |
541 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | |
542 | #define nNAK_TIMEOUT_H 0x0 | |
543 | ||
544 | /* Bit masks for USB_COUNT0 */ | |
545 | ||
546 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ | |
547 | ||
548 | /* Bit masks for USB_NAKLIMIT0 */ | |
549 | ||
550 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ | |
551 | ||
552 | /* Bit masks for USB_TX_MAX_PACKET */ | |
553 | ||
554 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ | |
555 | ||
556 | /* Bit masks for USB_RX_MAX_PACKET */ | |
557 | ||
558 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ | |
559 | ||
560 | /* Bit masks for USB_TXCSR */ | |
561 | ||
562 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | |
563 | #define nTXPKTRDY_T 0x0 | |
564 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | |
565 | #define nFIFO_NOT_EMPTY_T 0x0 | |
566 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | |
567 | #define nUNDERRUN_T 0x0 | |
568 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | |
569 | #define nFLUSHFIFO_T 0x0 | |
570 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | |
571 | #define nSTALL_SEND_T 0x0 | |
572 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | |
573 | #define nSTALL_SENT_T 0x0 | |
574 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | |
575 | #define nCLEAR_DATATOGGLE_T 0x0 | |
576 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | |
577 | #define nINCOMPTX_T 0x0 | |
578 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | |
579 | #define nDMAREQMODE_T 0x0 | |
580 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | |
581 | #define nFORCE_DATATOGGLE_T 0x0 | |
582 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | |
583 | #define nDMAREQ_ENA_T 0x0 | |
584 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | |
585 | #define nISO_T 0x0 | |
586 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | |
587 | #define nAUTOSET_T 0x0 | |
588 | #define ERROR_TH 0x4 /* error condition host mode */ | |
589 | #define nERROR_TH 0x0 | |
590 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | |
591 | #define nSTALL_RECEIVED_TH 0x0 | |
592 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | |
593 | #define nNAK_TIMEOUT_TH 0x0 | |
594 | ||
595 | /* Bit masks for USB_TXCOUNT */ | |
596 | ||
597 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ | |
598 | ||
599 | /* Bit masks for USB_RXCSR */ | |
600 | ||
601 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | |
602 | #define nRXPKTRDY_R 0x0 | |
603 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | |
604 | #define nFIFO_FULL_R 0x0 | |
605 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | |
606 | #define nOVERRUN_R 0x0 | |
607 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | |
608 | #define nDATAERROR_R 0x0 | |
609 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | |
610 | #define nFLUSHFIFO_R 0x0 | |
611 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | |
612 | #define nSTALL_SEND_R 0x0 | |
613 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | |
614 | #define nSTALL_SENT_R 0x0 | |
615 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | |
616 | #define nCLEAR_DATATOGGLE_R 0x0 | |
617 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | |
618 | #define nINCOMPRX_R 0x0 | |
619 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | |
620 | #define nDMAREQMODE_R 0x0 | |
621 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | |
622 | #define nDISNYET_R 0x0 | |
623 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | |
624 | #define nDMAREQ_ENA_R 0x0 | |
625 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | |
626 | #define nISO_R 0x0 | |
627 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | |
628 | #define nAUTOCLEAR_R 0x0 | |
629 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | |
630 | #define nERROR_RH 0x0 | |
631 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | |
632 | #define nREQPKT_RH 0x0 | |
633 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | |
634 | #define nSTALL_RECEIVED_RH 0x0 | |
635 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | |
636 | #define nINCOMPRX_RH 0x0 | |
637 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | |
638 | #define nDMAREQMODE_RH 0x0 | |
639 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | |
640 | #define nAUTOREQ_RH 0x0 | |
641 | ||
642 | /* Bit masks for USB_RXCOUNT */ | |
643 | ||
644 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ | |
645 | ||
646 | /* Bit masks for USB_TXTYPE */ | |
647 | ||
648 | #define TARGET_EP_NO_T 0xf /* EP number */ | |
649 | #define PROTOCOL_T 0xc /* transfer type */ | |
650 | ||
651 | /* Bit masks for USB_TXINTERVAL */ | |
652 | ||
653 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ | |
654 | ||
655 | /* Bit masks for USB_RXTYPE */ | |
656 | ||
657 | #define TARGET_EP_NO_R 0xf /* EP number */ | |
658 | #define PROTOCOL_R 0xc /* transfer type */ | |
659 | ||
660 | /* Bit masks for USB_RXINTERVAL */ | |
661 | ||
662 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ | |
663 | ||
664 | /* Bit masks for USB_DMA_INTERRUPT */ | |
665 | ||
666 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | |
667 | #define nDMA0_INT 0x0 | |
668 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | |
669 | #define nDMA1_INT 0x0 | |
670 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | |
671 | #define nDMA2_INT 0x0 | |
672 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | |
673 | #define nDMA3_INT 0x0 | |
674 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | |
675 | #define nDMA4_INT 0x0 | |
676 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | |
677 | #define nDMA5_INT 0x0 | |
678 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | |
679 | #define nDMA6_INT 0x0 | |
680 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | |
681 | #define nDMA7_INT 0x0 | |
682 | ||
683 | /* Bit masks for USB_DMAxCONTROL */ | |
684 | ||
685 | #define DMA_ENA 0x1 /* DMA enable */ | |
686 | #define nDMA_ENA 0x0 | |
687 | #define DIRECTION 0x2 /* direction of DMA transfer */ | |
688 | #define nDIRECTION 0x0 | |
689 | #define MODE 0x4 /* DMA Bus error */ | |
690 | #define nMODE 0x0 | |
691 | #define INT_ENA 0x8 /* Interrupt enable */ | |
692 | #define nINT_ENA 0x0 | |
693 | #define EPNUM 0xf0 /* EP number */ | |
694 | #define BUSERROR 0x100 /* DMA Bus error */ | |
695 | #define nBUSERROR 0x0 | |
696 | ||
697 | /* Bit masks for USB_DMAxADDRHIGH */ | |
698 | ||
699 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ | |
700 | ||
701 | /* Bit masks for USB_DMAxADDRLOW */ | |
702 | ||
703 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ | |
704 | ||
705 | /* Bit masks for USB_DMAxCOUNTHIGH */ | |
706 | ||
707 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ | |
708 | ||
709 | /* Bit masks for USB_DMAxCOUNTLOW */ | |
710 | ||
711 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ | |
712 | ||
713 | #endif /* _DEF_BF525_H */ |