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1 | /* |
2 | * File: include/asm-blackfin/mach-bf533/cdefBF532.h | |
3 | * Based on: | |
4 | * Author: | |
5 | * | |
6 | * Created: | |
7 | * Description: | |
8 | * | |
9 | * Rev: | |
10 | * | |
11 | * Modified: | |
12 | * | |
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2, or (at your option) | |
18 | * any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; see the file COPYING. | |
27 | * If not, write to the Free Software Foundation, | |
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
29 | */ | |
30 | ||
31 | #ifndef _CDEF_BF532_H | |
32 | #define _CDEF_BF532_H | |
33 | /* | |
34 | #if !defined(__ADSPLPBLACKFIN__) | |
35 | #warning cdefBF532.h should only be included for 532 compatible chips. | |
36 | #endif | |
37 | */ | |
38 | /*include all Core registers and bit definitions*/ | |
39 | #include "defBF532.h" | |
40 | ||
41 | /*include core specific register pointer definitions*/ | |
42 | #include <asm/mach-common/cdef_LPBlackfin.h> | |
43 | ||
44 | #include <asm/system.h> | |
45 | ||
46 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ | |
47 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | |
48 | #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) | |
49 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | |
50 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) | |
51 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | |
52 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) | |
53 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | |
1394f032 BW |
54 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
55 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | |
56 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | |
57 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | |
58 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | |
59 | { | |
60 | unsigned long flags, iwr; | |
61 | ||
1394f032 BW |
62 | /* Enable the PLL Wakeup bit in SIC IWR */ |
63 | iwr = bfin_read32(SIC_IWR); | |
64 | /* Only allow PPL Wakeup) */ | |
65 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | |
d1b945fd MH |
66 | |
67 | bfin_write16(VR_CTL, val); | |
68 | __builtin_bfin_ssync(); | |
69 | ||
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70 | local_irq_save(flags); |
71 | asm("IDLE;"); | |
72 | local_irq_restore(flags); | |
73 | bfin_write32(SIC_IWR, iwr); | |
74 | } | |
75 | ||
76 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ | |
19381f02 BW |
77 | #define bfin_read_SWRST() bfin_read16(SWRST) |
78 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) | |
79 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | |
80 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) | |
1394f032 BW |
81 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
82 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) | |
83 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | |
84 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) | |
85 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | |
86 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) | |
87 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | |
88 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) | |
89 | #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) | |
90 | #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) | |
91 | #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) | |
92 | #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val) | |
93 | #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) | |
94 | #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val) | |
95 | ||
96 | /* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ | |
97 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | |
98 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val) | |
99 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | |
100 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val) | |
101 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | |
102 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val) | |
103 | ||
104 | /* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ | |
105 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | |
106 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val) | |
107 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | |
108 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val) | |
109 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | |
110 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val) | |
111 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | |
112 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val) | |
113 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | |
114 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val) | |
115 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) | |
116 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val) | |
117 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | |
118 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) | |
119 | ||
19381f02 BW |
120 | /* DMA Traffic controls */ |
121 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | |
122 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) | |
123 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | |
124 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) | |
125 | ||
126 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | |
127 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | |
128 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) | |
129 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | |
130 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) | |
131 | ||
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132 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ |
133 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) | |
134 | #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) | |
135 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) | |
136 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val) | |
137 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) | |
138 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val) | |
139 | #define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) | |
140 | #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val) | |
141 | #define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) | |
142 | #define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val) | |
143 | #define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) | |
144 | #define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val) | |
145 | #define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) | |
146 | #define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val) | |
147 | #define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) | |
148 | #define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val) | |
149 | #define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) | |
150 | #define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val) | |
151 | #define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) | |
152 | #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val) | |
153 | #define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) | |
154 | #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val) | |
155 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) | |
156 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val) | |
157 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) | |
158 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val) | |
159 | #define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) | |
160 | #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val) | |
161 | #define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) | |
162 | #define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val) | |
163 | #define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) | |
164 | #define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val) | |
165 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) | |
166 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) | |
167 | ||
1394f032 BW |
168 | /* DMA Controller */ |
169 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | |
170 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) | |
171 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | |
172 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val) | |
173 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) | |
174 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val) | |
175 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | |
176 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val) | |
177 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | |
178 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val) | |
179 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | |
180 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val) | |
181 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | |
182 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val) | |
183 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) | |
184 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val) | |
185 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) | |
186 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val) | |
187 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | |
188 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val) | |
189 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | |
190 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val) | |
191 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | |
192 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val) | |
193 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | |
194 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val) | |
195 | ||
196 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | |
197 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val) | |
198 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | |
199 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val) | |
200 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) | |
201 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val) | |
202 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | |
203 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val) | |
204 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | |
205 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val) | |
206 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | |
207 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val) | |
208 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | |
209 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val) | |
210 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) | |
211 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val) | |
212 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) | |
213 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val) | |
214 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | |
215 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val) | |
216 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | |
217 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val) | |
218 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | |
219 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val) | |
220 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | |
221 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val) | |
222 | ||
223 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | |
224 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val) | |
225 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | |
226 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val) | |
227 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) | |
228 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val) | |
229 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | |
230 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val) | |
231 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | |
232 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val) | |
233 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | |
234 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val) | |
235 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | |
236 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val) | |
237 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) | |
238 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val) | |
239 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) | |
240 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val) | |
241 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | |
242 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val) | |
243 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | |
244 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val) | |
245 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | |
246 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val) | |
247 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | |
248 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val) | |
249 | ||
250 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | |
251 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val) | |
252 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | |
253 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val) | |
254 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) | |
255 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val) | |
256 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | |
257 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val) | |
258 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | |
259 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val) | |
260 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | |
261 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val) | |
262 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | |
263 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val) | |
264 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) | |
265 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val) | |
266 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) | |
267 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val) | |
268 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | |
269 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val) | |
270 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | |
271 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val) | |
272 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | |
273 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val) | |
274 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | |
275 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val) | |
276 | ||
277 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | |
278 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val) | |
279 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | |
280 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val) | |
281 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) | |
282 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val) | |
283 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | |
284 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val) | |
285 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | |
286 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val) | |
287 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | |
288 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val) | |
289 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | |
290 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val) | |
291 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) | |
292 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val) | |
293 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) | |
294 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val) | |
295 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | |
296 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val) | |
297 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | |
298 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val) | |
299 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | |
300 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val) | |
301 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | |
302 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val) | |
303 | ||
304 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | |
305 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val) | |
306 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | |
307 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val) | |
308 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) | |
309 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val) | |
310 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | |
311 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val) | |
312 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | |
313 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val) | |
314 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | |
315 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val) | |
316 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | |
317 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val) | |
318 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) | |
319 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val) | |
320 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) | |
321 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val) | |
322 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | |
323 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val) | |
324 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | |
325 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val) | |
326 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | |
327 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val) | |
328 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | |
329 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val) | |
330 | ||
331 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | |
332 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val) | |
333 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | |
334 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val) | |
335 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) | |
336 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val) | |
337 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | |
338 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val) | |
339 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | |
340 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val) | |
341 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | |
342 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val) | |
343 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | |
344 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val) | |
345 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) | |
346 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val) | |
347 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) | |
348 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val) | |
349 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | |
350 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val) | |
351 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | |
352 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val) | |
353 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | |
354 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val) | |
355 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | |
356 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val) | |
357 | ||
358 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | |
359 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val) | |
360 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | |
361 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val) | |
362 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) | |
363 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val) | |
364 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | |
365 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val) | |
366 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | |
367 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val) | |
368 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | |
369 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val) | |
370 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | |
371 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val) | |
372 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) | |
373 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val) | |
374 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) | |
375 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val) | |
376 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | |
377 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val) | |
378 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | |
379 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val) | |
380 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | |
381 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val) | |
382 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | |
383 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val) | |
384 | ||
385 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) | |
386 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) | |
387 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) | |
388 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) | |
389 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) | |
390 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) | |
391 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | |
392 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) | |
393 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) | |
394 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) | |
395 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | |
396 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) | |
397 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | |
398 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) | |
399 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) | |
400 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) | |
401 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) | |
402 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) | |
403 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) | |
404 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) | |
405 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) | |
406 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) | |
407 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) | |
408 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) | |
409 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) | |
410 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) | |
411 | ||
412 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) | |
413 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) | |
414 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) | |
415 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) | |
416 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) | |
417 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) | |
418 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | |
419 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) | |
420 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) | |
421 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) | |
422 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | |
423 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) | |
424 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | |
425 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) | |
426 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) | |
427 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) | |
428 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) | |
429 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) | |
430 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) | |
431 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) | |
432 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) | |
433 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) | |
434 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) | |
435 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) | |
436 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) | |
437 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) | |
438 | ||
439 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) | |
440 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) | |
441 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | |
442 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) | |
443 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) | |
444 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) | |
445 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) | |
446 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) | |
447 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) | |
448 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) | |
449 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) | |
450 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) | |
451 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) | |
452 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) | |
453 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) | |
454 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) | |
455 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) | |
456 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) | |
457 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) | |
458 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) | |
459 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) | |
460 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) | |
461 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) | |
462 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) | |
463 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) | |
464 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) | |
465 | ||
466 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) | |
467 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) | |
468 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) | |
469 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) | |
470 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) | |
471 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) | |
472 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) | |
473 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) | |
474 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) | |
475 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) | |
476 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) | |
477 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) | |
478 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) | |
479 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) | |
480 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) | |
481 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) | |
482 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) | |
483 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) | |
484 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) | |
485 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) | |
486 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) | |
487 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) | |
488 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) | |
489 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) | |
490 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) | |
491 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) | |
492 | ||
493 | /* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ | |
494 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | |
495 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) | |
496 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | |
497 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) | |
498 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | |
499 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) | |
500 | ||
501 | /* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ | |
502 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | |
503 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) | |
504 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | |
505 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) | |
506 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | |
507 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) | |
508 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) | |
509 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val) | |
510 | ||
511 | /* UART Controller */ | |
512 | #define bfin_read_UART_THR() bfin_read16(UART_THR) | |
513 | #define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) | |
514 | #define bfin_read_UART_RBR() bfin_read16(UART_RBR) | |
515 | #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) | |
516 | #define bfin_read_UART_DLL() bfin_read16(UART_DLL) | |
517 | #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) | |
518 | #define bfin_read_UART_IER() bfin_read16(UART_IER) | |
519 | #define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) | |
520 | #define bfin_read_UART_DLH() bfin_read16(UART_DLH) | |
521 | #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) | |
522 | #define bfin_read_UART_IIR() bfin_read16(UART_IIR) | |
523 | #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) | |
524 | #define bfin_read_UART_LCR() bfin_read16(UART_LCR) | |
525 | #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) | |
526 | #define bfin_read_UART_MCR() bfin_read16(UART_MCR) | |
527 | #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) | |
528 | #define bfin_read_UART_LSR() bfin_read16(UART_LSR) | |
529 | #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) | |
530 | /* | |
531 | #define UART_MSR | |
532 | */ | |
533 | #define bfin_read_UART_SCR() bfin_read16(UART_SCR) | |
534 | #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) | |
535 | #define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) | |
536 | #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) | |
537 | ||
538 | /* SPI Controller */ | |
539 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) | |
540 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) | |
541 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) | |
542 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) | |
543 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) | |
544 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) | |
545 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) | |
546 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) | |
547 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) | |
548 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) | |
549 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) | |
550 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) | |
551 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) | |
552 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) | |
553 | ||
554 | /* TIMER 0, 1, 2 Registers */ | |
555 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | |
556 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) | |
557 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | |
558 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) | |
559 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | |
560 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) | |
561 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | |
562 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) | |
563 | ||
564 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | |
565 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) | |
566 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | |
567 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) | |
568 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | |
569 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) | |
570 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | |
571 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) | |
572 | ||
573 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | |
574 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) | |
575 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | |
576 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) | |
577 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | |
578 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) | |
579 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | |
580 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) | |
581 | ||
582 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) | |
583 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val) | |
584 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) | |
585 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val) | |
586 | #define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) | |
587 | #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val) | |
588 | ||
589 | /* SPORT0 Controller */ | |
590 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | |
591 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) | |
592 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | |
593 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) | |
594 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | |
595 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) | |
596 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | |
597 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) | |
598 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | |
599 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) | |
600 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | |
601 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) | |
602 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) | |
603 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) | |
604 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) | |
605 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) | |
606 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) | |
607 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) | |
608 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) | |
609 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) | |
610 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | |
611 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) | |
612 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | |
613 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) | |
614 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | |
615 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) | |
616 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | |
617 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) | |
618 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | |
619 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) | |
620 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | |
621 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) | |
622 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | |
623 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) | |
624 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | |
625 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) | |
626 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | |
627 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) | |
628 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | |
629 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) | |
630 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | |
631 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) | |
632 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | |
633 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) | |
634 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | |
635 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) | |
636 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | |
637 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) | |
638 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | |
639 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) | |
640 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | |
641 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) | |
642 | ||
643 | /* SPORT1 Controller */ | |
644 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | |
645 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) | |
646 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | |
647 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) | |
648 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | |
649 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) | |
650 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | |
651 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) | |
652 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | |
653 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) | |
654 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | |
655 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) | |
656 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) | |
657 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) | |
658 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) | |
659 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) | |
660 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) | |
661 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) | |
662 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) | |
663 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) | |
664 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | |
665 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) | |
666 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | |
667 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) | |
668 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | |
669 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) | |
670 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | |
671 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) | |
672 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | |
673 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) | |
674 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | |
675 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) | |
676 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | |
677 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) | |
678 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | |
679 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) | |
680 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | |
681 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) | |
682 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | |
683 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) | |
684 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | |
685 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) | |
686 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | |
687 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) | |
688 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | |
689 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) | |
690 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | |
691 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) | |
692 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | |
693 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) | |
694 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | |
695 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) | |
696 | ||
697 | /* Parallel Peripheral Interface (PPI) */ | |
698 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | |
699 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val) | |
700 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | |
701 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val) | |
702 | #define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() | |
703 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | |
704 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val) | |
705 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | |
706 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val) | |
707 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | |
708 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) | |
709 | ||
710 | #endif /* _CDEF_BF532_H */ |