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088eec11 RH |
1 | |
2 | /* | |
3 | * File: include/asm-blackfin/mach-bf548/anomaly.h | |
4 | * Based on: | |
5 | * Author: | |
6 | * | |
7 | * Created: | |
8 | * Description: | |
9 | * | |
10 | * Rev: | |
11 | * | |
12 | * Modified: | |
13 | * | |
14 | * | |
15 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; see the file COPYING. | |
29 | * If not, write to the Free Software Foundation, | |
30 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
31 | */ | |
32 | ||
33 | #ifndef _MACH_ANOMALY_H_ | |
34 | #define _MACH_ANOMALY_H_ | |
35 | #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in | |
36 | slot1 and store of a P register in slot 2 is not | |
37 | supported */ | |
38 | #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive | |
39 | Channel DMA stops */ | |
40 | #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR | |
41 | registers. */ | |
42 | #define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the | |
43 | Shadow of a Conditional Branch */ | |
44 | #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event | |
45 | interrupt not functional */ | |
46 | #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on | |
47 | SPORT external receive and transmit clocks. */ | |
48 | #define ANOMALY_05000272 /* Certain data cache write through modes fail for | |
49 | VDDint <=0.9V */ | |
24a07a12 RH |
50 | #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is |
51 | not restored */ | |
088eec11 RH |
52 | #define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the |
53 | Boundary of Reserved Memory */ | |
54 | #define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and | |
55 | LC Registers Are Interrupted */ | |
56 | #define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ | |
57 | #define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ | |
58 | #define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to | |
59 | the USB FIFO Simultaneously */ | |
60 | #define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() | |
61 | function */ | |
62 | #define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional | |
63 | */ | |
64 | #define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ | |
65 | #define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM | |
66 | Skew */ | |
67 | #define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ | |
68 | #define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration | |
69 | of Host DMA Port */ | |
70 | #define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent | |
71 | Allowed Configuration on Host DMA Port */ | |
72 | #define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ | |
73 | ||
74 | #endif /* _MACH_ANOMALY_H_ */ |