Commit | Line | Data |
---|---|---|
51533b61 MS |
1 | #ifndef __ata_defs_h |
2 | #define __ata_defs_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/ata/rtl/ata_regs.r | |
7 | * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp | |
8 | * last modfied: Mon Apr 11 16:06:25 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r | |
11 | * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | /* Main access macros */ | |
17 | #ifndef REG_RD | |
18 | #define REG_RD( scope, inst, reg ) \ | |
19 | REG_READ( reg_##scope##_##reg, \ | |
20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_WR | |
24 | #define REG_WR( scope, inst, reg, val ) \ | |
25 | REG_WRITE( reg_##scope##_##reg, \ | |
26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_RD_VECT | |
30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
31 | REG_READ( reg_##scope##_##reg, \ | |
32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
33 | (index) * STRIDE_##scope##_##reg ) | |
34 | #endif | |
35 | ||
36 | #ifndef REG_WR_VECT | |
37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
38 | REG_WRITE( reg_##scope##_##reg, \ | |
39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
40 | (index) * STRIDE_##scope##_##reg, (val) ) | |
41 | #endif | |
42 | ||
43 | #ifndef REG_RD_INT | |
44 | #define REG_RD_INT( scope, inst, reg ) \ | |
45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_WR_INT | |
49 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
51 | #endif | |
52 | ||
53 | #ifndef REG_RD_INT_VECT | |
54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
56 | (index) * STRIDE_##scope##_##reg ) | |
57 | #endif | |
58 | ||
59 | #ifndef REG_WR_INT_VECT | |
60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
62 | (index) * STRIDE_##scope##_##reg, (val) ) | |
63 | #endif | |
64 | ||
65 | #ifndef REG_TYPE_CONV | |
66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
68 | #endif | |
69 | ||
70 | #ifndef reg_page_size | |
71 | #define reg_page_size 8192 | |
72 | #endif | |
73 | ||
74 | #ifndef REG_ADDR | |
75 | #define REG_ADDR( scope, inst, reg ) \ | |
76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
77 | #endif | |
78 | ||
79 | #ifndef REG_ADDR_VECT | |
80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
82 | (index) * STRIDE_##scope##_##reg ) | |
83 | #endif | |
84 | ||
85 | /* C-code for register scope ata */ | |
86 | ||
87 | /* Register rw_ctrl0, scope ata, type rw */ | |
88 | typedef struct { | |
89 | unsigned int pio_hold : 6; | |
90 | unsigned int pio_strb : 6; | |
91 | unsigned int pio_setup : 6; | |
92 | unsigned int dma_hold : 6; | |
93 | unsigned int dma_strb : 6; | |
94 | unsigned int rst : 1; | |
95 | unsigned int en : 1; | |
96 | } reg_ata_rw_ctrl0; | |
97 | #define REG_RD_ADDR_ata_rw_ctrl0 12 | |
98 | #define REG_WR_ADDR_ata_rw_ctrl0 12 | |
99 | ||
100 | /* Register rw_ctrl1, scope ata, type rw */ | |
101 | typedef struct { | |
102 | unsigned int udma_tcyc : 4; | |
103 | unsigned int udma_tdvs : 4; | |
104 | unsigned int dummy1 : 24; | |
105 | } reg_ata_rw_ctrl1; | |
106 | #define REG_RD_ADDR_ata_rw_ctrl1 16 | |
107 | #define REG_WR_ADDR_ata_rw_ctrl1 16 | |
108 | ||
109 | /* Register rw_ctrl2, scope ata, type rw */ | |
110 | typedef struct { | |
111 | unsigned int data : 16; | |
112 | unsigned int dummy1 : 3; | |
113 | unsigned int dma_size : 1; | |
114 | unsigned int multi : 1; | |
115 | unsigned int hsh : 2; | |
116 | unsigned int trf_mode : 1; | |
117 | unsigned int rw : 1; | |
118 | unsigned int addr : 3; | |
119 | unsigned int cs0 : 1; | |
120 | unsigned int cs1 : 1; | |
121 | unsigned int sel : 2; | |
122 | } reg_ata_rw_ctrl2; | |
123 | #define REG_RD_ADDR_ata_rw_ctrl2 0 | |
124 | #define REG_WR_ADDR_ata_rw_ctrl2 0 | |
125 | ||
126 | /* Register rs_stat_data, scope ata, type rs */ | |
127 | typedef struct { | |
128 | unsigned int data : 16; | |
129 | unsigned int dav : 1; | |
130 | unsigned int busy : 1; | |
131 | unsigned int dummy1 : 14; | |
132 | } reg_ata_rs_stat_data; | |
133 | #define REG_RD_ADDR_ata_rs_stat_data 4 | |
134 | ||
135 | /* Register r_stat_data, scope ata, type r */ | |
136 | typedef struct { | |
137 | unsigned int data : 16; | |
138 | unsigned int dav : 1; | |
139 | unsigned int busy : 1; | |
140 | unsigned int dummy1 : 14; | |
141 | } reg_ata_r_stat_data; | |
142 | #define REG_RD_ADDR_ata_r_stat_data 8 | |
143 | ||
144 | /* Register rw_trf_cnt, scope ata, type rw */ | |
145 | typedef struct { | |
146 | unsigned int cnt : 17; | |
147 | unsigned int dummy1 : 15; | |
148 | } reg_ata_rw_trf_cnt; | |
149 | #define REG_RD_ADDR_ata_rw_trf_cnt 20 | |
150 | #define REG_WR_ADDR_ata_rw_trf_cnt 20 | |
151 | ||
152 | /* Register r_stat_misc, scope ata, type r */ | |
153 | typedef struct { | |
154 | unsigned int crc : 16; | |
155 | unsigned int dummy1 : 16; | |
156 | } reg_ata_r_stat_misc; | |
157 | #define REG_RD_ADDR_ata_r_stat_misc 24 | |
158 | ||
159 | /* Register rw_intr_mask, scope ata, type rw */ | |
160 | typedef struct { | |
161 | unsigned int bus0 : 1; | |
162 | unsigned int bus1 : 1; | |
163 | unsigned int bus2 : 1; | |
164 | unsigned int bus3 : 1; | |
165 | unsigned int dummy1 : 28; | |
166 | } reg_ata_rw_intr_mask; | |
167 | #define REG_RD_ADDR_ata_rw_intr_mask 28 | |
168 | #define REG_WR_ADDR_ata_rw_intr_mask 28 | |
169 | ||
170 | /* Register rw_ack_intr, scope ata, type rw */ | |
171 | typedef struct { | |
172 | unsigned int bus0 : 1; | |
173 | unsigned int bus1 : 1; | |
174 | unsigned int bus2 : 1; | |
175 | unsigned int bus3 : 1; | |
176 | unsigned int dummy1 : 28; | |
177 | } reg_ata_rw_ack_intr; | |
178 | #define REG_RD_ADDR_ata_rw_ack_intr 32 | |
179 | #define REG_WR_ADDR_ata_rw_ack_intr 32 | |
180 | ||
181 | /* Register r_intr, scope ata, type r */ | |
182 | typedef struct { | |
183 | unsigned int bus0 : 1; | |
184 | unsigned int bus1 : 1; | |
185 | unsigned int bus2 : 1; | |
186 | unsigned int bus3 : 1; | |
187 | unsigned int dummy1 : 28; | |
188 | } reg_ata_r_intr; | |
189 | #define REG_RD_ADDR_ata_r_intr 36 | |
190 | ||
191 | /* Register r_masked_intr, scope ata, type r */ | |
192 | typedef struct { | |
193 | unsigned int bus0 : 1; | |
194 | unsigned int bus1 : 1; | |
195 | unsigned int bus2 : 1; | |
196 | unsigned int bus3 : 1; | |
197 | unsigned int dummy1 : 28; | |
198 | } reg_ata_r_masked_intr; | |
199 | #define REG_RD_ADDR_ata_r_masked_intr 40 | |
200 | ||
201 | ||
202 | /* Constants */ | |
203 | enum { | |
204 | regk_ata_active = 0x00000001, | |
205 | regk_ata_byte = 0x00000001, | |
206 | regk_ata_data = 0x00000001, | |
207 | regk_ata_dma = 0x00000001, | |
208 | regk_ata_inactive = 0x00000000, | |
209 | regk_ata_no = 0x00000000, | |
210 | regk_ata_nodata = 0x00000000, | |
211 | regk_ata_pio = 0x00000000, | |
212 | regk_ata_rd = 0x00000001, | |
213 | regk_ata_reg = 0x00000000, | |
214 | regk_ata_rw_ctrl0_default = 0x00000000, | |
215 | regk_ata_rw_ctrl2_default = 0x00000000, | |
216 | regk_ata_rw_intr_mask_default = 0x00000000, | |
217 | regk_ata_udma = 0x00000002, | |
218 | regk_ata_word = 0x00000000, | |
219 | regk_ata_wr = 0x00000000, | |
220 | regk_ata_yes = 0x00000001 | |
221 | }; | |
222 | #endif /* __ata_defs_h */ |