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51533b61 MS |
1 | #ifndef __iop_spu_defs_asm_h |
2 | #define __iop_spu_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/io_proc/rtl/iop_spu.r | |
7 | * id: <not found> | |
8 | * last modfied: Mon Apr 11 16:08:46 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r | |
11 | * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | ||
17 | #ifndef REG_FIELD | |
18 | #define REG_FIELD( scope, reg, field, value ) \ | |
19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_STATE | |
24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
26 | #define REG_STATE_X_( k, shift ) (k << shift) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_MASK | |
30 | #define REG_MASK( scope, reg, field ) \ | |
31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
33 | #endif | |
34 | ||
35 | #ifndef REG_LSB | |
36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
37 | #endif | |
38 | ||
39 | #ifndef REG_BIT | |
40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
41 | #endif | |
42 | ||
43 | #ifndef REG_ADDR | |
44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_ADDR_VECT | |
49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
51 | STRIDE_##scope##_##reg ) | |
52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
53 | ((inst) + offs + (index) * stride) | |
54 | #endif | |
55 | ||
56 | #define STRIDE_iop_spu_rw_r 4 | |
57 | /* Register rw_r, scope iop_spu, type rw */ | |
58 | #define reg_iop_spu_rw_r_offset 0 | |
59 | ||
60 | /* Register rw_seq_pc, scope iop_spu, type rw */ | |
61 | #define reg_iop_spu_rw_seq_pc___addr___lsb 0 | |
62 | #define reg_iop_spu_rw_seq_pc___addr___width 12 | |
63 | #define reg_iop_spu_rw_seq_pc_offset 64 | |
64 | ||
65 | /* Register rw_fsm_pc, scope iop_spu, type rw */ | |
66 | #define reg_iop_spu_rw_fsm_pc___addr___lsb 0 | |
67 | #define reg_iop_spu_rw_fsm_pc___addr___width 12 | |
68 | #define reg_iop_spu_rw_fsm_pc_offset 68 | |
69 | ||
70 | /* Register rw_ctrl, scope iop_spu, type rw */ | |
71 | #define reg_iop_spu_rw_ctrl___fsm___lsb 0 | |
72 | #define reg_iop_spu_rw_ctrl___fsm___width 1 | |
73 | #define reg_iop_spu_rw_ctrl___fsm___bit 0 | |
74 | #define reg_iop_spu_rw_ctrl___en___lsb 1 | |
75 | #define reg_iop_spu_rw_ctrl___en___width 1 | |
76 | #define reg_iop_spu_rw_ctrl___en___bit 1 | |
77 | #define reg_iop_spu_rw_ctrl_offset 72 | |
78 | ||
79 | /* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ | |
80 | #define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 | |
81 | #define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 | |
82 | #define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 | |
83 | #define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 | |
84 | #define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 | |
85 | #define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 | |
86 | #define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 | |
87 | #define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 | |
88 | #define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 | |
89 | #define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 | |
90 | #define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 | |
91 | #define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 | |
92 | #define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 | |
93 | #define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 | |
94 | #define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 | |
95 | #define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 | |
96 | #define reg_iop_spu_rw_fsm_inputs3_0_offset 76 | |
97 | ||
98 | /* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ | |
99 | #define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 | |
100 | #define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 | |
101 | #define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 | |
102 | #define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 | |
103 | #define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 | |
104 | #define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 | |
105 | #define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 | |
106 | #define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 | |
107 | #define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 | |
108 | #define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 | |
109 | #define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 | |
110 | #define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 | |
111 | #define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 | |
112 | #define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 | |
113 | #define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 | |
114 | #define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 | |
115 | #define reg_iop_spu_rw_fsm_inputs7_4_offset 80 | |
116 | ||
117 | /* Register rw_gio_out, scope iop_spu, type rw */ | |
118 | #define reg_iop_spu_rw_gio_out_offset 84 | |
119 | ||
120 | /* Register rw_bus0_out, scope iop_spu, type rw */ | |
121 | #define reg_iop_spu_rw_bus0_out_offset 88 | |
122 | ||
123 | /* Register rw_bus1_out, scope iop_spu, type rw */ | |
124 | #define reg_iop_spu_rw_bus1_out_offset 92 | |
125 | ||
126 | /* Register r_gio_in, scope iop_spu, type r */ | |
127 | #define reg_iop_spu_r_gio_in_offset 96 | |
128 | ||
129 | /* Register r_bus0_in, scope iop_spu, type r */ | |
130 | #define reg_iop_spu_r_bus0_in_offset 100 | |
131 | ||
132 | /* Register r_bus1_in, scope iop_spu, type r */ | |
133 | #define reg_iop_spu_r_bus1_in_offset 104 | |
134 | ||
135 | /* Register rw_gio_out_set, scope iop_spu, type rw */ | |
136 | #define reg_iop_spu_rw_gio_out_set_offset 108 | |
137 | ||
138 | /* Register rw_gio_out_clr, scope iop_spu, type rw */ | |
139 | #define reg_iop_spu_rw_gio_out_clr_offset 112 | |
140 | ||
141 | /* Register rs_wr_stat, scope iop_spu, type rs */ | |
142 | #define reg_iop_spu_rs_wr_stat___r0___lsb 0 | |
143 | #define reg_iop_spu_rs_wr_stat___r0___width 1 | |
144 | #define reg_iop_spu_rs_wr_stat___r0___bit 0 | |
145 | #define reg_iop_spu_rs_wr_stat___r1___lsb 1 | |
146 | #define reg_iop_spu_rs_wr_stat___r1___width 1 | |
147 | #define reg_iop_spu_rs_wr_stat___r1___bit 1 | |
148 | #define reg_iop_spu_rs_wr_stat___r2___lsb 2 | |
149 | #define reg_iop_spu_rs_wr_stat___r2___width 1 | |
150 | #define reg_iop_spu_rs_wr_stat___r2___bit 2 | |
151 | #define reg_iop_spu_rs_wr_stat___r3___lsb 3 | |
152 | #define reg_iop_spu_rs_wr_stat___r3___width 1 | |
153 | #define reg_iop_spu_rs_wr_stat___r3___bit 3 | |
154 | #define reg_iop_spu_rs_wr_stat___r4___lsb 4 | |
155 | #define reg_iop_spu_rs_wr_stat___r4___width 1 | |
156 | #define reg_iop_spu_rs_wr_stat___r4___bit 4 | |
157 | #define reg_iop_spu_rs_wr_stat___r5___lsb 5 | |
158 | #define reg_iop_spu_rs_wr_stat___r5___width 1 | |
159 | #define reg_iop_spu_rs_wr_stat___r5___bit 5 | |
160 | #define reg_iop_spu_rs_wr_stat___r6___lsb 6 | |
161 | #define reg_iop_spu_rs_wr_stat___r6___width 1 | |
162 | #define reg_iop_spu_rs_wr_stat___r6___bit 6 | |
163 | #define reg_iop_spu_rs_wr_stat___r7___lsb 7 | |
164 | #define reg_iop_spu_rs_wr_stat___r7___width 1 | |
165 | #define reg_iop_spu_rs_wr_stat___r7___bit 7 | |
166 | #define reg_iop_spu_rs_wr_stat___r8___lsb 8 | |
167 | #define reg_iop_spu_rs_wr_stat___r8___width 1 | |
168 | #define reg_iop_spu_rs_wr_stat___r8___bit 8 | |
169 | #define reg_iop_spu_rs_wr_stat___r9___lsb 9 | |
170 | #define reg_iop_spu_rs_wr_stat___r9___width 1 | |
171 | #define reg_iop_spu_rs_wr_stat___r9___bit 9 | |
172 | #define reg_iop_spu_rs_wr_stat___r10___lsb 10 | |
173 | #define reg_iop_spu_rs_wr_stat___r10___width 1 | |
174 | #define reg_iop_spu_rs_wr_stat___r10___bit 10 | |
175 | #define reg_iop_spu_rs_wr_stat___r11___lsb 11 | |
176 | #define reg_iop_spu_rs_wr_stat___r11___width 1 | |
177 | #define reg_iop_spu_rs_wr_stat___r11___bit 11 | |
178 | #define reg_iop_spu_rs_wr_stat___r12___lsb 12 | |
179 | #define reg_iop_spu_rs_wr_stat___r12___width 1 | |
180 | #define reg_iop_spu_rs_wr_stat___r12___bit 12 | |
181 | #define reg_iop_spu_rs_wr_stat___r13___lsb 13 | |
182 | #define reg_iop_spu_rs_wr_stat___r13___width 1 | |
183 | #define reg_iop_spu_rs_wr_stat___r13___bit 13 | |
184 | #define reg_iop_spu_rs_wr_stat___r14___lsb 14 | |
185 | #define reg_iop_spu_rs_wr_stat___r14___width 1 | |
186 | #define reg_iop_spu_rs_wr_stat___r14___bit 14 | |
187 | #define reg_iop_spu_rs_wr_stat___r15___lsb 15 | |
188 | #define reg_iop_spu_rs_wr_stat___r15___width 1 | |
189 | #define reg_iop_spu_rs_wr_stat___r15___bit 15 | |
190 | #define reg_iop_spu_rs_wr_stat_offset 116 | |
191 | ||
192 | /* Register r_wr_stat, scope iop_spu, type r */ | |
193 | #define reg_iop_spu_r_wr_stat___r0___lsb 0 | |
194 | #define reg_iop_spu_r_wr_stat___r0___width 1 | |
195 | #define reg_iop_spu_r_wr_stat___r0___bit 0 | |
196 | #define reg_iop_spu_r_wr_stat___r1___lsb 1 | |
197 | #define reg_iop_spu_r_wr_stat___r1___width 1 | |
198 | #define reg_iop_spu_r_wr_stat___r1___bit 1 | |
199 | #define reg_iop_spu_r_wr_stat___r2___lsb 2 | |
200 | #define reg_iop_spu_r_wr_stat___r2___width 1 | |
201 | #define reg_iop_spu_r_wr_stat___r2___bit 2 | |
202 | #define reg_iop_spu_r_wr_stat___r3___lsb 3 | |
203 | #define reg_iop_spu_r_wr_stat___r3___width 1 | |
204 | #define reg_iop_spu_r_wr_stat___r3___bit 3 | |
205 | #define reg_iop_spu_r_wr_stat___r4___lsb 4 | |
206 | #define reg_iop_spu_r_wr_stat___r4___width 1 | |
207 | #define reg_iop_spu_r_wr_stat___r4___bit 4 | |
208 | #define reg_iop_spu_r_wr_stat___r5___lsb 5 | |
209 | #define reg_iop_spu_r_wr_stat___r5___width 1 | |
210 | #define reg_iop_spu_r_wr_stat___r5___bit 5 | |
211 | #define reg_iop_spu_r_wr_stat___r6___lsb 6 | |
212 | #define reg_iop_spu_r_wr_stat___r6___width 1 | |
213 | #define reg_iop_spu_r_wr_stat___r6___bit 6 | |
214 | #define reg_iop_spu_r_wr_stat___r7___lsb 7 | |
215 | #define reg_iop_spu_r_wr_stat___r7___width 1 | |
216 | #define reg_iop_spu_r_wr_stat___r7___bit 7 | |
217 | #define reg_iop_spu_r_wr_stat___r8___lsb 8 | |
218 | #define reg_iop_spu_r_wr_stat___r8___width 1 | |
219 | #define reg_iop_spu_r_wr_stat___r8___bit 8 | |
220 | #define reg_iop_spu_r_wr_stat___r9___lsb 9 | |
221 | #define reg_iop_spu_r_wr_stat___r9___width 1 | |
222 | #define reg_iop_spu_r_wr_stat___r9___bit 9 | |
223 | #define reg_iop_spu_r_wr_stat___r10___lsb 10 | |
224 | #define reg_iop_spu_r_wr_stat___r10___width 1 | |
225 | #define reg_iop_spu_r_wr_stat___r10___bit 10 | |
226 | #define reg_iop_spu_r_wr_stat___r11___lsb 11 | |
227 | #define reg_iop_spu_r_wr_stat___r11___width 1 | |
228 | #define reg_iop_spu_r_wr_stat___r11___bit 11 | |
229 | #define reg_iop_spu_r_wr_stat___r12___lsb 12 | |
230 | #define reg_iop_spu_r_wr_stat___r12___width 1 | |
231 | #define reg_iop_spu_r_wr_stat___r12___bit 12 | |
232 | #define reg_iop_spu_r_wr_stat___r13___lsb 13 | |
233 | #define reg_iop_spu_r_wr_stat___r13___width 1 | |
234 | #define reg_iop_spu_r_wr_stat___r13___bit 13 | |
235 | #define reg_iop_spu_r_wr_stat___r14___lsb 14 | |
236 | #define reg_iop_spu_r_wr_stat___r14___width 1 | |
237 | #define reg_iop_spu_r_wr_stat___r14___bit 14 | |
238 | #define reg_iop_spu_r_wr_stat___r15___lsb 15 | |
239 | #define reg_iop_spu_r_wr_stat___r15___width 1 | |
240 | #define reg_iop_spu_r_wr_stat___r15___bit 15 | |
241 | #define reg_iop_spu_r_wr_stat_offset 120 | |
242 | ||
243 | /* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ | |
244 | #define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 | |
245 | ||
246 | /* Register r_stat_in, scope iop_spu, type r */ | |
247 | #define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 | |
248 | #define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 | |
249 | #define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 | |
250 | #define reg_iop_spu_r_stat_in___fifo_out_last___width 1 | |
251 | #define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 | |
252 | #define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 | |
253 | #define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 | |
254 | #define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 | |
255 | #define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 | |
256 | #define reg_iop_spu_r_stat_in___fifo_out_all___width 1 | |
257 | #define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 | |
258 | #define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 | |
259 | #define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 | |
260 | #define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 | |
261 | #define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 | |
262 | #define reg_iop_spu_r_stat_in___dmc_out_all___width 1 | |
263 | #define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 | |
264 | #define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 | |
265 | #define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 | |
266 | #define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 | |
267 | #define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 | |
268 | #define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 | |
269 | #define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 | |
270 | #define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 | |
271 | #define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 | |
272 | #define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 | |
273 | #define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 | |
274 | #define reg_iop_spu_r_stat_in___dmc_out_last___width 1 | |
275 | #define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 | |
276 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 | |
277 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 | |
278 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 | |
279 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 | |
280 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 | |
281 | #define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 | |
282 | #define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 | |
283 | #define reg_iop_spu_r_stat_in___pcrc_correct___width 1 | |
284 | #define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 | |
285 | #define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 | |
286 | #define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 | |
287 | #define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 | |
288 | #define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 | |
289 | #define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 | |
290 | #define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 | |
291 | #define reg_iop_spu_r_stat_in___dmc_in_full___width 1 | |
292 | #define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 | |
293 | #define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 | |
294 | #define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 | |
295 | #define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 | |
296 | #define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 | |
297 | #define reg_iop_spu_r_stat_in___spu_gio_out___width 4 | |
298 | #define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 | |
299 | #define reg_iop_spu_r_stat_in___sync_clk12___width 1 | |
300 | #define reg_iop_spu_r_stat_in___sync_clk12___bit 27 | |
301 | #define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 | |
302 | #define reg_iop_spu_r_stat_in___scrc_out_data___width 1 | |
303 | #define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 | |
304 | #define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 | |
305 | #define reg_iop_spu_r_stat_in___scrc_in_err___width 1 | |
306 | #define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 | |
307 | #define reg_iop_spu_r_stat_in___mc_busy___lsb 30 | |
308 | #define reg_iop_spu_r_stat_in___mc_busy___width 1 | |
309 | #define reg_iop_spu_r_stat_in___mc_busy___bit 30 | |
310 | #define reg_iop_spu_r_stat_in___mc_owned___lsb 31 | |
311 | #define reg_iop_spu_r_stat_in___mc_owned___width 1 | |
312 | #define reg_iop_spu_r_stat_in___mc_owned___bit 31 | |
313 | #define reg_iop_spu_r_stat_in_offset 128 | |
314 | ||
315 | /* Register r_trigger_in, scope iop_spu, type r */ | |
316 | #define reg_iop_spu_r_trigger_in_offset 132 | |
317 | ||
318 | /* Register r_special_stat, scope iop_spu, type r */ | |
319 | #define reg_iop_spu_r_special_stat___c_flag___lsb 0 | |
320 | #define reg_iop_spu_r_special_stat___c_flag___width 1 | |
321 | #define reg_iop_spu_r_special_stat___c_flag___bit 0 | |
322 | #define reg_iop_spu_r_special_stat___v_flag___lsb 1 | |
323 | #define reg_iop_spu_r_special_stat___v_flag___width 1 | |
324 | #define reg_iop_spu_r_special_stat___v_flag___bit 1 | |
325 | #define reg_iop_spu_r_special_stat___z_flag___lsb 2 | |
326 | #define reg_iop_spu_r_special_stat___z_flag___width 1 | |
327 | #define reg_iop_spu_r_special_stat___z_flag___bit 2 | |
328 | #define reg_iop_spu_r_special_stat___n_flag___lsb 3 | |
329 | #define reg_iop_spu_r_special_stat___n_flag___width 1 | |
330 | #define reg_iop_spu_r_special_stat___n_flag___bit 3 | |
331 | #define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 | |
332 | #define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 | |
333 | #define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 | |
334 | #define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 | |
335 | #define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 | |
336 | #define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 | |
337 | #define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 | |
338 | #define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 | |
339 | #define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 | |
340 | #define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 | |
341 | #define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 | |
342 | #define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 | |
343 | #define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 | |
344 | #define reg_iop_spu_r_special_stat___fsm_in0___width 1 | |
345 | #define reg_iop_spu_r_special_stat___fsm_in0___bit 8 | |
346 | #define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 | |
347 | #define reg_iop_spu_r_special_stat___fsm_in1___width 1 | |
348 | #define reg_iop_spu_r_special_stat___fsm_in1___bit 9 | |
349 | #define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 | |
350 | #define reg_iop_spu_r_special_stat___fsm_in2___width 1 | |
351 | #define reg_iop_spu_r_special_stat___fsm_in2___bit 10 | |
352 | #define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 | |
353 | #define reg_iop_spu_r_special_stat___fsm_in3___width 1 | |
354 | #define reg_iop_spu_r_special_stat___fsm_in3___bit 11 | |
355 | #define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 | |
356 | #define reg_iop_spu_r_special_stat___fsm_in4___width 1 | |
357 | #define reg_iop_spu_r_special_stat___fsm_in4___bit 12 | |
358 | #define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 | |
359 | #define reg_iop_spu_r_special_stat___fsm_in5___width 1 | |
360 | #define reg_iop_spu_r_special_stat___fsm_in5___bit 13 | |
361 | #define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 | |
362 | #define reg_iop_spu_r_special_stat___fsm_in6___width 1 | |
363 | #define reg_iop_spu_r_special_stat___fsm_in6___bit 14 | |
364 | #define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 | |
365 | #define reg_iop_spu_r_special_stat___fsm_in7___width 1 | |
366 | #define reg_iop_spu_r_special_stat___fsm_in7___bit 15 | |
367 | #define reg_iop_spu_r_special_stat___event0___lsb 16 | |
368 | #define reg_iop_spu_r_special_stat___event0___width 1 | |
369 | #define reg_iop_spu_r_special_stat___event0___bit 16 | |
370 | #define reg_iop_spu_r_special_stat___event1___lsb 17 | |
371 | #define reg_iop_spu_r_special_stat___event1___width 1 | |
372 | #define reg_iop_spu_r_special_stat___event1___bit 17 | |
373 | #define reg_iop_spu_r_special_stat___event2___lsb 18 | |
374 | #define reg_iop_spu_r_special_stat___event2___width 1 | |
375 | #define reg_iop_spu_r_special_stat___event2___bit 18 | |
376 | #define reg_iop_spu_r_special_stat___event3___lsb 19 | |
377 | #define reg_iop_spu_r_special_stat___event3___width 1 | |
378 | #define reg_iop_spu_r_special_stat___event3___bit 19 | |
379 | #define reg_iop_spu_r_special_stat_offset 136 | |
380 | ||
381 | /* Register rw_reg_access, scope iop_spu, type rw */ | |
382 | #define reg_iop_spu_rw_reg_access___addr___lsb 0 | |
383 | #define reg_iop_spu_rw_reg_access___addr___width 13 | |
384 | #define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 | |
385 | #define reg_iop_spu_rw_reg_access___imm_hi___width 16 | |
386 | #define reg_iop_spu_rw_reg_access_offset 140 | |
387 | ||
388 | #define STRIDE_iop_spu_rw_event_cfg 4 | |
389 | /* Register rw_event_cfg, scope iop_spu, type rw */ | |
390 | #define reg_iop_spu_rw_event_cfg___addr___lsb 0 | |
391 | #define reg_iop_spu_rw_event_cfg___addr___width 12 | |
392 | #define reg_iop_spu_rw_event_cfg___src___lsb 12 | |
393 | #define reg_iop_spu_rw_event_cfg___src___width 2 | |
394 | #define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 | |
395 | #define reg_iop_spu_rw_event_cfg___eq_en___width 1 | |
396 | #define reg_iop_spu_rw_event_cfg___eq_en___bit 14 | |
397 | #define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 | |
398 | #define reg_iop_spu_rw_event_cfg___eq_inv___width 1 | |
399 | #define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 | |
400 | #define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 | |
401 | #define reg_iop_spu_rw_event_cfg___gt_en___width 1 | |
402 | #define reg_iop_spu_rw_event_cfg___gt_en___bit 16 | |
403 | #define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 | |
404 | #define reg_iop_spu_rw_event_cfg___gt_inv___width 1 | |
405 | #define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 | |
406 | #define reg_iop_spu_rw_event_cfg_offset 144 | |
407 | ||
408 | #define STRIDE_iop_spu_rw_event_mask 4 | |
409 | /* Register rw_event_mask, scope iop_spu, type rw */ | |
410 | #define reg_iop_spu_rw_event_mask_offset 160 | |
411 | ||
412 | #define STRIDE_iop_spu_rw_event_val 4 | |
413 | /* Register rw_event_val, scope iop_spu, type rw */ | |
414 | #define reg_iop_spu_rw_event_val_offset 176 | |
415 | ||
416 | /* Register rw_event_ret, scope iop_spu, type rw */ | |
417 | #define reg_iop_spu_rw_event_ret___addr___lsb 0 | |
418 | #define reg_iop_spu_rw_event_ret___addr___width 12 | |
419 | #define reg_iop_spu_rw_event_ret_offset 192 | |
420 | ||
421 | /* Register r_trace, scope iop_spu, type r */ | |
422 | #define reg_iop_spu_r_trace___fsm___lsb 0 | |
423 | #define reg_iop_spu_r_trace___fsm___width 1 | |
424 | #define reg_iop_spu_r_trace___fsm___bit 0 | |
425 | #define reg_iop_spu_r_trace___en___lsb 1 | |
426 | #define reg_iop_spu_r_trace___en___width 1 | |
427 | #define reg_iop_spu_r_trace___en___bit 1 | |
428 | #define reg_iop_spu_r_trace___c_flag___lsb 2 | |
429 | #define reg_iop_spu_r_trace___c_flag___width 1 | |
430 | #define reg_iop_spu_r_trace___c_flag___bit 2 | |
431 | #define reg_iop_spu_r_trace___v_flag___lsb 3 | |
432 | #define reg_iop_spu_r_trace___v_flag___width 1 | |
433 | #define reg_iop_spu_r_trace___v_flag___bit 3 | |
434 | #define reg_iop_spu_r_trace___z_flag___lsb 4 | |
435 | #define reg_iop_spu_r_trace___z_flag___width 1 | |
436 | #define reg_iop_spu_r_trace___z_flag___bit 4 | |
437 | #define reg_iop_spu_r_trace___n_flag___lsb 5 | |
438 | #define reg_iop_spu_r_trace___n_flag___width 1 | |
439 | #define reg_iop_spu_r_trace___n_flag___bit 5 | |
440 | #define reg_iop_spu_r_trace___seq_addr___lsb 6 | |
441 | #define reg_iop_spu_r_trace___seq_addr___width 12 | |
442 | #define reg_iop_spu_r_trace___fsm_addr___lsb 20 | |
443 | #define reg_iop_spu_r_trace___fsm_addr___width 12 | |
444 | #define reg_iop_spu_r_trace_offset 196 | |
445 | ||
446 | /* Register r_fsm_trace, scope iop_spu, type r */ | |
447 | #define reg_iop_spu_r_fsm_trace___fsm___lsb 0 | |
448 | #define reg_iop_spu_r_fsm_trace___fsm___width 1 | |
449 | #define reg_iop_spu_r_fsm_trace___fsm___bit 0 | |
450 | #define reg_iop_spu_r_fsm_trace___en___lsb 1 | |
451 | #define reg_iop_spu_r_fsm_trace___en___width 1 | |
452 | #define reg_iop_spu_r_fsm_trace___en___bit 1 | |
453 | #define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 | |
454 | #define reg_iop_spu_r_fsm_trace___tmr_done___width 1 | |
455 | #define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 | |
456 | #define reg_iop_spu_r_fsm_trace___inp0___lsb 3 | |
457 | #define reg_iop_spu_r_fsm_trace___inp0___width 1 | |
458 | #define reg_iop_spu_r_fsm_trace___inp0___bit 3 | |
459 | #define reg_iop_spu_r_fsm_trace___inp1___lsb 4 | |
460 | #define reg_iop_spu_r_fsm_trace___inp1___width 1 | |
461 | #define reg_iop_spu_r_fsm_trace___inp1___bit 4 | |
462 | #define reg_iop_spu_r_fsm_trace___inp2___lsb 5 | |
463 | #define reg_iop_spu_r_fsm_trace___inp2___width 1 | |
464 | #define reg_iop_spu_r_fsm_trace___inp2___bit 5 | |
465 | #define reg_iop_spu_r_fsm_trace___inp3___lsb 6 | |
466 | #define reg_iop_spu_r_fsm_trace___inp3___width 1 | |
467 | #define reg_iop_spu_r_fsm_trace___inp3___bit 6 | |
468 | #define reg_iop_spu_r_fsm_trace___event0___lsb 7 | |
469 | #define reg_iop_spu_r_fsm_trace___event0___width 1 | |
470 | #define reg_iop_spu_r_fsm_trace___event0___bit 7 | |
471 | #define reg_iop_spu_r_fsm_trace___event1___lsb 8 | |
472 | #define reg_iop_spu_r_fsm_trace___event1___width 1 | |
473 | #define reg_iop_spu_r_fsm_trace___event1___bit 8 | |
474 | #define reg_iop_spu_r_fsm_trace___event2___lsb 9 | |
475 | #define reg_iop_spu_r_fsm_trace___event2___width 1 | |
476 | #define reg_iop_spu_r_fsm_trace___event2___bit 9 | |
477 | #define reg_iop_spu_r_fsm_trace___event3___lsb 10 | |
478 | #define reg_iop_spu_r_fsm_trace___event3___width 1 | |
479 | #define reg_iop_spu_r_fsm_trace___event3___bit 10 | |
480 | #define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 | |
481 | #define reg_iop_spu_r_fsm_trace___gio_out___width 8 | |
482 | #define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 | |
483 | #define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 | |
484 | #define reg_iop_spu_r_fsm_trace_offset 200 | |
485 | ||
486 | #define STRIDE_iop_spu_rw_brp 4 | |
487 | /* Register rw_brp, scope iop_spu, type rw */ | |
488 | #define reg_iop_spu_rw_brp___addr___lsb 0 | |
489 | #define reg_iop_spu_rw_brp___addr___width 12 | |
490 | #define reg_iop_spu_rw_brp___fsm___lsb 12 | |
491 | #define reg_iop_spu_rw_brp___fsm___width 1 | |
492 | #define reg_iop_spu_rw_brp___fsm___bit 12 | |
493 | #define reg_iop_spu_rw_brp___en___lsb 13 | |
494 | #define reg_iop_spu_rw_brp___en___width 1 | |
495 | #define reg_iop_spu_rw_brp___en___bit 13 | |
496 | #define reg_iop_spu_rw_brp_offset 204 | |
497 | ||
498 | ||
499 | /* Constants */ | |
500 | #define regk_iop_spu_attn_hi 0x00000005 | |
501 | #define regk_iop_spu_attn_lo 0x00000005 | |
502 | #define regk_iop_spu_attn_r0 0x00000000 | |
503 | #define regk_iop_spu_attn_r1 0x00000001 | |
504 | #define regk_iop_spu_attn_r10 0x00000002 | |
505 | #define regk_iop_spu_attn_r11 0x00000003 | |
506 | #define regk_iop_spu_attn_r12 0x00000004 | |
507 | #define regk_iop_spu_attn_r13 0x00000005 | |
508 | #define regk_iop_spu_attn_r14 0x00000006 | |
509 | #define regk_iop_spu_attn_r15 0x00000007 | |
510 | #define regk_iop_spu_attn_r2 0x00000002 | |
511 | #define regk_iop_spu_attn_r3 0x00000003 | |
512 | #define regk_iop_spu_attn_r4 0x00000004 | |
513 | #define regk_iop_spu_attn_r5 0x00000005 | |
514 | #define regk_iop_spu_attn_r6 0x00000006 | |
515 | #define regk_iop_spu_attn_r7 0x00000007 | |
516 | #define regk_iop_spu_attn_r8 0x00000000 | |
517 | #define regk_iop_spu_attn_r9 0x00000001 | |
518 | #define regk_iop_spu_c 0x00000000 | |
519 | #define regk_iop_spu_flag 0x00000002 | |
520 | #define regk_iop_spu_gio_in 0x00000000 | |
521 | #define regk_iop_spu_gio_out 0x00000005 | |
522 | #define regk_iop_spu_gio_out0 0x00000008 | |
523 | #define regk_iop_spu_gio_out1 0x00000009 | |
524 | #define regk_iop_spu_gio_out2 0x0000000a | |
525 | #define regk_iop_spu_gio_out3 0x0000000b | |
526 | #define regk_iop_spu_gio_out4 0x0000000c | |
527 | #define regk_iop_spu_gio_out5 0x0000000d | |
528 | #define regk_iop_spu_gio_out6 0x0000000e | |
529 | #define regk_iop_spu_gio_out7 0x0000000f | |
530 | #define regk_iop_spu_n 0x00000003 | |
531 | #define regk_iop_spu_no 0x00000000 | |
532 | #define regk_iop_spu_r0 0x00000008 | |
533 | #define regk_iop_spu_r1 0x00000009 | |
534 | #define regk_iop_spu_r10 0x0000000a | |
535 | #define regk_iop_spu_r11 0x0000000b | |
536 | #define regk_iop_spu_r12 0x0000000c | |
537 | #define regk_iop_spu_r13 0x0000000d | |
538 | #define regk_iop_spu_r14 0x0000000e | |
539 | #define regk_iop_spu_r15 0x0000000f | |
540 | #define regk_iop_spu_r2 0x0000000a | |
541 | #define regk_iop_spu_r3 0x0000000b | |
542 | #define regk_iop_spu_r4 0x0000000c | |
543 | #define regk_iop_spu_r5 0x0000000d | |
544 | #define regk_iop_spu_r6 0x0000000e | |
545 | #define regk_iop_spu_r7 0x0000000f | |
546 | #define regk_iop_spu_r8 0x00000008 | |
547 | #define regk_iop_spu_r9 0x00000009 | |
548 | #define regk_iop_spu_reg_hi 0x00000002 | |
549 | #define regk_iop_spu_reg_lo 0x00000002 | |
550 | #define regk_iop_spu_rw_brp_default 0x00000000 | |
551 | #define regk_iop_spu_rw_brp_size 0x00000004 | |
552 | #define regk_iop_spu_rw_ctrl_default 0x00000000 | |
553 | #define regk_iop_spu_rw_event_cfg_size 0x00000004 | |
554 | #define regk_iop_spu_rw_event_mask_size 0x00000004 | |
555 | #define regk_iop_spu_rw_event_val_size 0x00000004 | |
556 | #define regk_iop_spu_rw_gio_out_default 0x00000000 | |
557 | #define regk_iop_spu_rw_r_size 0x00000010 | |
558 | #define regk_iop_spu_rw_reg_access_default 0x00000000 | |
559 | #define regk_iop_spu_stat_in 0x00000002 | |
560 | #define regk_iop_spu_statin_hi 0x00000004 | |
561 | #define regk_iop_spu_statin_lo 0x00000004 | |
562 | #define regk_iop_spu_trig 0x00000003 | |
563 | #define regk_iop_spu_trigger 0x00000006 | |
564 | #define regk_iop_spu_v 0x00000001 | |
565 | #define regk_iop_spu_wsts_gioout_spec 0x00000001 | |
566 | #define regk_iop_spu_xor 0x00000003 | |
567 | #define regk_iop_spu_xor_bus0_r2_0 0x00000000 | |
568 | #define regk_iop_spu_xor_bus0m_r2_0 0x00000002 | |
569 | #define regk_iop_spu_xor_bus1_r3_0 0x00000001 | |
570 | #define regk_iop_spu_xor_bus1m_r3_0 0x00000003 | |
571 | #define regk_iop_spu_yes 0x00000001 | |
572 | #define regk_iop_spu_z 0x00000002 | |
573 | #endif /* __iop_spu_defs_asm_h */ |