Commit | Line | Data |
---|---|---|
51533b61 MS |
1 | #ifndef __iop_fifo_in_defs_h |
2 | #define __iop_fifo_in_defs_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/io_proc/rtl/iop_fifo_in.r | |
7 | * id: <not found> | |
8 | * last modfied: Mon Apr 11 16:10:07 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r | |
11 | * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | /* Main access macros */ | |
17 | #ifndef REG_RD | |
18 | #define REG_RD( scope, inst, reg ) \ | |
19 | REG_READ( reg_##scope##_##reg, \ | |
20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_WR | |
24 | #define REG_WR( scope, inst, reg, val ) \ | |
25 | REG_WRITE( reg_##scope##_##reg, \ | |
26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_RD_VECT | |
30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
31 | REG_READ( reg_##scope##_##reg, \ | |
32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
33 | (index) * STRIDE_##scope##_##reg ) | |
34 | #endif | |
35 | ||
36 | #ifndef REG_WR_VECT | |
37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
38 | REG_WRITE( reg_##scope##_##reg, \ | |
39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
40 | (index) * STRIDE_##scope##_##reg, (val) ) | |
41 | #endif | |
42 | ||
43 | #ifndef REG_RD_INT | |
44 | #define REG_RD_INT( scope, inst, reg ) \ | |
45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_WR_INT | |
49 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
51 | #endif | |
52 | ||
53 | #ifndef REG_RD_INT_VECT | |
54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
56 | (index) * STRIDE_##scope##_##reg ) | |
57 | #endif | |
58 | ||
59 | #ifndef REG_WR_INT_VECT | |
60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
62 | (index) * STRIDE_##scope##_##reg, (val) ) | |
63 | #endif | |
64 | ||
65 | #ifndef REG_TYPE_CONV | |
66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
68 | #endif | |
69 | ||
70 | #ifndef reg_page_size | |
71 | #define reg_page_size 8192 | |
72 | #endif | |
73 | ||
74 | #ifndef REG_ADDR | |
75 | #define REG_ADDR( scope, inst, reg ) \ | |
76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
77 | #endif | |
78 | ||
79 | #ifndef REG_ADDR_VECT | |
80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
82 | (index) * STRIDE_##scope##_##reg ) | |
83 | #endif | |
84 | ||
85 | /* C-code for register scope iop_fifo_in */ | |
86 | ||
87 | /* Register rw_cfg, scope iop_fifo_in, type rw */ | |
88 | typedef struct { | |
89 | unsigned int avail_lim : 3; | |
90 | unsigned int byte_order : 2; | |
91 | unsigned int trig : 2; | |
92 | unsigned int last_dis_dif_in : 1; | |
93 | unsigned int mode : 2; | |
94 | unsigned int dummy1 : 22; | |
95 | } reg_iop_fifo_in_rw_cfg; | |
96 | #define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 | |
97 | #define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 | |
98 | ||
99 | /* Register rw_ctrl, scope iop_fifo_in, type rw */ | |
100 | typedef struct { | |
101 | unsigned int dif_in_en : 1; | |
102 | unsigned int dif_out_en : 1; | |
103 | unsigned int dummy1 : 30; | |
104 | } reg_iop_fifo_in_rw_ctrl; | |
105 | #define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 | |
106 | #define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 | |
107 | ||
108 | /* Register r_stat, scope iop_fifo_in, type r */ | |
109 | typedef struct { | |
110 | unsigned int avail_bytes : 4; | |
111 | unsigned int last : 8; | |
112 | unsigned int dif_in_en : 1; | |
113 | unsigned int dif_out_en : 1; | |
114 | unsigned int dummy1 : 18; | |
115 | } reg_iop_fifo_in_r_stat; | |
116 | #define REG_RD_ADDR_iop_fifo_in_r_stat 8 | |
117 | ||
118 | /* Register rs_rd1byte, scope iop_fifo_in, type rs */ | |
119 | typedef struct { | |
120 | unsigned int data : 8; | |
121 | unsigned int dummy1 : 24; | |
122 | } reg_iop_fifo_in_rs_rd1byte; | |
123 | #define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 | |
124 | ||
125 | /* Register r_rd1byte, scope iop_fifo_in, type r */ | |
126 | typedef struct { | |
127 | unsigned int data : 8; | |
128 | unsigned int dummy1 : 24; | |
129 | } reg_iop_fifo_in_r_rd1byte; | |
130 | #define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 | |
131 | ||
132 | /* Register rs_rd2byte, scope iop_fifo_in, type rs */ | |
133 | typedef struct { | |
134 | unsigned int data : 16; | |
135 | unsigned int dummy1 : 16; | |
136 | } reg_iop_fifo_in_rs_rd2byte; | |
137 | #define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 | |
138 | ||
139 | /* Register r_rd2byte, scope iop_fifo_in, type r */ | |
140 | typedef struct { | |
141 | unsigned int data : 16; | |
142 | unsigned int dummy1 : 16; | |
143 | } reg_iop_fifo_in_r_rd2byte; | |
144 | #define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 | |
145 | ||
146 | /* Register rs_rd3byte, scope iop_fifo_in, type rs */ | |
147 | typedef struct { | |
148 | unsigned int data : 24; | |
149 | unsigned int dummy1 : 8; | |
150 | } reg_iop_fifo_in_rs_rd3byte; | |
151 | #define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 | |
152 | ||
153 | /* Register r_rd3byte, scope iop_fifo_in, type r */ | |
154 | typedef struct { | |
155 | unsigned int data : 24; | |
156 | unsigned int dummy1 : 8; | |
157 | } reg_iop_fifo_in_r_rd3byte; | |
158 | #define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 | |
159 | ||
160 | /* Register rs_rd4byte, scope iop_fifo_in, type rs */ | |
161 | typedef struct { | |
162 | unsigned int data : 32; | |
163 | } reg_iop_fifo_in_rs_rd4byte; | |
164 | #define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 | |
165 | ||
166 | /* Register r_rd4byte, scope iop_fifo_in, type r */ | |
167 | typedef struct { | |
168 | unsigned int data : 32; | |
169 | } reg_iop_fifo_in_r_rd4byte; | |
170 | #define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 | |
171 | ||
172 | /* Register rw_set_last, scope iop_fifo_in, type rw */ | |
173 | typedef unsigned int reg_iop_fifo_in_rw_set_last; | |
174 | #define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 | |
175 | #define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 | |
176 | ||
177 | /* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ | |
178 | typedef struct { | |
179 | unsigned int last : 2; | |
180 | unsigned int dummy1 : 30; | |
181 | } reg_iop_fifo_in_rw_strb_dif_in; | |
182 | #define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 | |
183 | #define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 | |
184 | ||
185 | /* Register rw_intr_mask, scope iop_fifo_in, type rw */ | |
186 | typedef struct { | |
187 | unsigned int urun : 1; | |
188 | unsigned int last_data : 1; | |
189 | unsigned int dav : 1; | |
190 | unsigned int avail : 1; | |
191 | unsigned int orun : 1; | |
192 | unsigned int dummy1 : 27; | |
193 | } reg_iop_fifo_in_rw_intr_mask; | |
194 | #define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 | |
195 | #define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 | |
196 | ||
197 | /* Register rw_ack_intr, scope iop_fifo_in, type rw */ | |
198 | typedef struct { | |
199 | unsigned int urun : 1; | |
200 | unsigned int last_data : 1; | |
201 | unsigned int dav : 1; | |
202 | unsigned int avail : 1; | |
203 | unsigned int orun : 1; | |
204 | unsigned int dummy1 : 27; | |
205 | } reg_iop_fifo_in_rw_ack_intr; | |
206 | #define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 | |
207 | #define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 | |
208 | ||
209 | /* Register r_intr, scope iop_fifo_in, type r */ | |
210 | typedef struct { | |
211 | unsigned int urun : 1; | |
212 | unsigned int last_data : 1; | |
213 | unsigned int dav : 1; | |
214 | unsigned int avail : 1; | |
215 | unsigned int orun : 1; | |
216 | unsigned int dummy1 : 27; | |
217 | } reg_iop_fifo_in_r_intr; | |
218 | #define REG_RD_ADDR_iop_fifo_in_r_intr 60 | |
219 | ||
220 | /* Register r_masked_intr, scope iop_fifo_in, type r */ | |
221 | typedef struct { | |
222 | unsigned int urun : 1; | |
223 | unsigned int last_data : 1; | |
224 | unsigned int dav : 1; | |
225 | unsigned int avail : 1; | |
226 | unsigned int orun : 1; | |
227 | unsigned int dummy1 : 27; | |
228 | } reg_iop_fifo_in_r_masked_intr; | |
229 | #define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 | |
230 | ||
231 | ||
232 | /* Constants */ | |
233 | enum { | |
234 | regk_iop_fifo_in_dif_in = 0x00000002, | |
235 | regk_iop_fifo_in_hi = 0x00000000, | |
236 | regk_iop_fifo_in_neg = 0x00000002, | |
237 | regk_iop_fifo_in_no = 0x00000000, | |
238 | regk_iop_fifo_in_order16 = 0x00000001, | |
239 | regk_iop_fifo_in_order24 = 0x00000002, | |
240 | regk_iop_fifo_in_order32 = 0x00000003, | |
241 | regk_iop_fifo_in_order8 = 0x00000000, | |
242 | regk_iop_fifo_in_pos = 0x00000001, | |
243 | regk_iop_fifo_in_pos_neg = 0x00000003, | |
244 | regk_iop_fifo_in_rw_cfg_default = 0x00000024, | |
245 | regk_iop_fifo_in_rw_ctrl_default = 0x00000000, | |
246 | regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, | |
247 | regk_iop_fifo_in_rw_set_last_default = 0x00000000, | |
248 | regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, | |
249 | regk_iop_fifo_in_size16 = 0x00000002, | |
250 | regk_iop_fifo_in_size24 = 0x00000001, | |
251 | regk_iop_fifo_in_size32 = 0x00000000, | |
252 | regk_iop_fifo_in_size8 = 0x00000003, | |
253 | regk_iop_fifo_in_yes = 0x00000001 | |
254 | }; | |
255 | #endif /* __iop_fifo_in_defs_h */ |