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Merge commit 'v2.6.28-rc2' into x86/pci-ioapic-boot-irq-quirks
[deliverable/linux.git] / include / asm-cris / arch-v32 / mach-a3 / hwregs / intr_vect_defs.h
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JN		 1#ifndef __intr_vect_defs_h
2#define __intr_vect_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: intr_vect.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope intr_vect */
83
84
85#define STRIDE_intr_vect_rw_mask 4
86/* Register rw_mask0, scope intr_vect, type rw */
87typedef struct {
88 unsigned int timer0 : 1;
89 unsigned int timer1 : 1;
90 unsigned int dma0 : 1;
91 unsigned int dma1 : 1;
92 unsigned int dma2 : 1;
93 unsigned int dma3 : 1;
94 unsigned int dma4 : 1;
95 unsigned int dma5 : 1;
96 unsigned int dma6 : 1;
97 unsigned int dma7 : 1;
98 unsigned int dma9 : 1;
99 unsigned int dma11 : 1;
100 unsigned int gio : 1;
101 unsigned int iop0 : 1;
102 unsigned int iop1 : 1;
103 unsigned int ser0 : 1;
104 unsigned int ser1 : 1;
105 unsigned int ser2 : 1;
106 unsigned int ser3 : 1;
107 unsigned int ser4 : 1;
108 unsigned int sser : 1;
109 unsigned int strdma0 : 1;
110 unsigned int strdma1 : 1;
111 unsigned int strdma2 : 1;
112 unsigned int strdma3 : 1;
113 unsigned int strdma5 : 1;
114 unsigned int vin : 1;
115 unsigned int vout : 1;
116 unsigned int jpeg : 1;
117 unsigned int h264 : 1;
118 unsigned int histo : 1;
119 unsigned int ccd : 1;
120} reg_intr_vect_rw_mask0;
121#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
122#define REG_RD_ADDR_intr_vect_rw_mask 0
123#define REG_WR_ADDR_intr_vect_rw_mask 0
124#define REG_RD_ADDR_intr_vect_rw_mask0 0
125#define REG_WR_ADDR_intr_vect_rw_mask0 0
126
127#define STRIDE_intr_vect_r_vect 4
128/* Register r_vect0, scope intr_vect, type r */
129typedef struct {
130 unsigned int timer0 : 1;
131 unsigned int timer1 : 1;
132 unsigned int dma0 : 1;
133 unsigned int dma1 : 1;
134 unsigned int dma2 : 1;
135 unsigned int dma3 : 1;
136 unsigned int dma4 : 1;
137 unsigned int dma5 : 1;
138 unsigned int dma6 : 1;
139 unsigned int dma7 : 1;
140 unsigned int dma9 : 1;
141 unsigned int dma11 : 1;
142 unsigned int gio : 1;
143 unsigned int iop0 : 1;
144 unsigned int iop1 : 1;
145 unsigned int ser0 : 1;
146 unsigned int ser1 : 1;
147 unsigned int ser2 : 1;
148 unsigned int ser3 : 1;
149 unsigned int ser4 : 1;
150 unsigned int sser : 1;
151 unsigned int strdma0 : 1;
152 unsigned int strdma1 : 1;
153 unsigned int strdma2 : 1;
154 unsigned int strdma3 : 1;
155 unsigned int strdma5 : 1;
156 unsigned int vin : 1;
157 unsigned int vout : 1;
158 unsigned int jpeg : 1;
159 unsigned int h264 : 1;
160 unsigned int histo : 1;
161 unsigned int ccd : 1;
162} reg_intr_vect_r_vect0;
163#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
164#define REG_RD_ADDR_intr_vect_r_vect 8
165#define REG_RD_ADDR_intr_vect_r_vect0 8
166
167#define STRIDE_intr_vect_r_masked_vect 4
168/* Register r_masked_vect0, scope intr_vect, type r */
169typedef struct {
170 unsigned int timer0 : 1;
171 unsigned int timer1 : 1;
172 unsigned int dma0 : 1;
173 unsigned int dma1 : 1;
174 unsigned int dma2 : 1;
175 unsigned int dma3 : 1;
176 unsigned int dma4 : 1;
177 unsigned int dma5 : 1;
178 unsigned int dma6 : 1;
179 unsigned int dma7 : 1;
180 unsigned int dma9 : 1;
181 unsigned int dma11 : 1;
182 unsigned int gio : 1;
183 unsigned int iop0 : 1;
184 unsigned int iop1 : 1;
185 unsigned int ser0 : 1;
186 unsigned int ser1 : 1;
187 unsigned int ser2 : 1;
188 unsigned int ser3 : 1;
189 unsigned int ser4 : 1;
190 unsigned int sser : 1;
191 unsigned int strdma0 : 1;
192 unsigned int strdma1 : 1;
193 unsigned int strdma2 : 1;
194 unsigned int strdma3 : 1;
195 unsigned int strdma5 : 1;
196 unsigned int vin : 1;
197 unsigned int vout : 1;
198 unsigned int jpeg : 1;
199 unsigned int h264 : 1;
200 unsigned int histo : 1;
201 unsigned int ccd : 1;
202} reg_intr_vect_r_masked_vect0;
203#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
204#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
205#define REG_RD_ADDR_intr_vect_r_masked_vect 16
206
207#define STRIDE_intr_vect_rw_xmask 4
208/* Register rw_xmask0, scope intr_vect, type rw */
209typedef struct {
210 unsigned int timer0 : 1;
211 unsigned int timer1 : 1;
212 unsigned int dma0 : 1;
213 unsigned int dma1 : 1;
214 unsigned int dma2 : 1;
215 unsigned int dma3 : 1;
216 unsigned int dma4 : 1;
217 unsigned int dma5 : 1;
218 unsigned int dma6 : 1;
219 unsigned int dma7 : 1;
220 unsigned int dma9 : 1;
221 unsigned int dma11 : 1;
222 unsigned int gio : 1;
223 unsigned int iop0 : 1;
224 unsigned int iop1 : 1;
225 unsigned int ser0 : 1;
226 unsigned int ser1 : 1;
227 unsigned int ser2 : 1;
228 unsigned int ser3 : 1;
229 unsigned int ser4 : 1;
230 unsigned int sser : 1;
231 unsigned int strdma0 : 1;
232 unsigned int strdma1 : 1;
233 unsigned int strdma2 : 1;
234 unsigned int strdma3 : 1;
235 unsigned int strdma5 : 1;
236 unsigned int vin : 1;
237 unsigned int vout : 1;
238 unsigned int jpeg : 1;
239 unsigned int h264 : 1;
240 unsigned int histo : 1;
241 unsigned int ccd : 1;
242} reg_intr_vect_rw_xmask0;
243#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
244#define REG_RD_ADDR_intr_vect_rw_xmask0 24
245#define REG_WR_ADDR_intr_vect_rw_xmask0 24
246#define REG_RD_ADDR_intr_vect_rw_xmask 24
247#define REG_WR_ADDR_intr_vect_rw_xmask 24
248
249/* Register rw_mask1, scope intr_vect, type rw */
250typedef struct {
251 unsigned int eth : 1;
252 unsigned int memarb_bar : 1;
253 unsigned int memarb_foo : 1;
254 unsigned int pio : 1;
255 unsigned int sclr : 1;
256 unsigned int sclr_fifo : 1;
257 unsigned int dummy1 : 26;
258} reg_intr_vect_rw_mask1;
259#define REG_RD_ADDR_intr_vect_rw_mask1 4
260#define REG_WR_ADDR_intr_vect_rw_mask1 4
261
262/* Register r_vect1, scope intr_vect, type r */
263typedef struct {
264 unsigned int eth : 1;
265 unsigned int memarb_bar : 1;
266 unsigned int memarb_foo : 1;
267 unsigned int pio : 1;
268 unsigned int sclr : 1;
269 unsigned int sclr_fifo : 1;
270 unsigned int dummy1 : 26;
271} reg_intr_vect_r_vect1;
272#define REG_RD_ADDR_intr_vect_r_vect1 12
273
274/* Register r_masked_vect1, scope intr_vect, type r */
275typedef struct {
276 unsigned int eth : 1;
277 unsigned int memarb_bar : 1;
278 unsigned int memarb_foo : 1;
279 unsigned int pio : 1;
280 unsigned int sclr : 1;
281 unsigned int sclr_fifo : 1;
282 unsigned int dummy1 : 26;
283} reg_intr_vect_r_masked_vect1;
284#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
285
286/* Register rw_xmask1, scope intr_vect, type rw */
287typedef struct {
288 unsigned int eth : 1;
289 unsigned int memarb_bar : 1;
290 unsigned int memarb_foo : 1;
291 unsigned int pio : 1;
292 unsigned int sclr : 1;
293 unsigned int sclr_fifo : 1;
294 unsigned int dummy1 : 26;
295} reg_intr_vect_rw_xmask1;
296#define REG_RD_ADDR_intr_vect_rw_xmask1 28
297#define REG_WR_ADDR_intr_vect_rw_xmask1 28
298
299/* Register rw_xmask_ctrl, scope intr_vect, type rw */
300typedef struct {
301 unsigned int en : 1;
302 unsigned int dummy1 : 31;
303} reg_intr_vect_rw_xmask_ctrl;
304#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
305#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
306
307/* Register r_nmi, scope intr_vect, type r */
308typedef struct {
309 unsigned int watchdog0 : 1;
310 unsigned int watchdog1 : 1;
311 unsigned int dummy1 : 30;
312} reg_intr_vect_r_nmi;
313#define REG_RD_ADDR_intr_vect_r_nmi 64
314
315/* Register r_guru, scope intr_vect, type r */
316typedef struct {
317 unsigned int jtag : 1;
318 unsigned int dummy1 : 31;
319} reg_intr_vect_r_guru;
320#define REG_RD_ADDR_intr_vect_r_guru 68
321
322
323/* Register rw_ipi, scope intr_vect, type rw */
324typedef struct
325{
326 unsigned int vector;
327} reg_intr_vect_rw_ipi;
328#define REG_RD_ADDR_intr_vect_rw_ipi 72
329#define REG_WR_ADDR_intr_vect_rw_ipi 72
330
331/* Constants */
332enum {
333 regk_intr_vect_no = 0x00000000,
334 regk_intr_vect_rw_mask0_default = 0x00000000,
335 regk_intr_vect_rw_mask1_default = 0x00000000,
336 regk_intr_vect_rw_xmask0_default = 0x00000000,
337 regk_intr_vect_rw_xmask1_default = 0x00000000,
338 regk_intr_vect_rw_xmask_ctrl_default = 0x00000000,
339 regk_intr_vect_yes = 0x00000001
340};
341#endif /* __intr_vect_defs_h */
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