[deliverable/linux.git] / include / asm-frv / atomic.h

/* atomic.h: atomic operation emulation for FR-V
 *
 * For an explanation of how atomic ops work in this arch, see:
 *   Documentation/frv/atomic-ops.txt
 *
 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H

#include <linux/types.h>
#include <asm/spr-regs.h>
#include <asm/system.h>

#ifdef CONFIG_SMP
#error not SMP safe
#endif

/*
 * Atomic operations that C can't guarantee us.  Useful for
 * resource counting etc..
 *
 * We do not have SMP systems, so we don't have to deal with that.
 */

/* Atomic operations are already serializing */
#define smp_mb__before_atomic_dec()	barrier()
#define smp_mb__after_atomic_dec()	barrier()
#define smp_mb__before_atomic_inc()	barrier()
#define smp_mb__after_atomic_inc()	barrier()

#define ATOMIC_INIT(i)		{ (i) }
#define atomic_read(v)		((v)->counter)
#define atomic_set(v, i)	(((v)->counter) = (i))

#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
static inline int atomic_add_return(int i, atomic_t *v)
{
	unsigned long val;

	asm("0:						\n"
	    "	orcc		gr0,gr0,gr0,icc3	\n"	/* set ICC3.Z */
	    "	ckeq		icc3,cc7		\n"
	    "	ld.p		%M0,%1			\n"	/* LD.P/ORCR must be atomic */
	    "	orcr		cc7,cc7,cc3		\n"	/* set CC3 to true */
	    "	add%I2		%1,%2,%1		\n"
	    "	cst.p		%1,%M0		,cc3,#1	\n"
	    "	corcc		gr29,gr29,gr0	,cc3,#1	\n"	/* clear ICC3.Z if store happens */
	    "	beq		icc3,#0,0b		\n"
	    : "+U"(v->counter), "=&r"(val)
	    : "NPr"(i)
	    : "memory", "cc7", "cc3", "icc3"
	    );

	return val;
}

static inline int atomic_sub_return(int i, atomic_t *v)
{
	unsigned long val;

	asm("0:						\n"
	    "	orcc		gr0,gr0,gr0,icc3	\n"	/* set ICC3.Z */
	    "	ckeq		icc3,cc7		\n"
	    "	ld.p		%M0,%1			\n"	/* LD.P/ORCR must be atomic */
	    "	orcr		cc7,cc7,cc3		\n"	/* set CC3 to true */
	    "	sub%I2		%1,%2,%1		\n"
	    "	cst.p		%1,%M0		,cc3,#1	\n"
	    "	corcc		gr29,gr29,gr0	,cc3,#1	\n"	/* clear ICC3.Z if store happens */
	    "	beq		icc3,#0,0b		\n"
	    : "+U"(v->counter), "=&r"(val)
	    : "NPr"(i)
	    : "memory", "cc7", "cc3", "icc3"
	    );

	return val;
}

#else

extern int atomic_add_return(int i, atomic_t *v);
extern int atomic_sub_return(int i, atomic_t *v);

#endif

static inline int atomic_add_negative(int i, atomic_t *v)
{
	return atomic_add_return(i, v) < 0;
}

static inline void atomic_add(int i, atomic_t *v)
{
	atomic_add_return(i, v);
}

static inline void atomic_sub(int i, atomic_t *v)
{
	atomic_sub_return(i, v);
}

static inline void atomic_inc(atomic_t *v)
{
	atomic_add_return(1, v);
}

static inline void atomic_dec(atomic_t *v)
{
	atomic_sub_return(1, v);
}

#define atomic_dec_return(v)		atomic_sub_return(1, (v))
#define atomic_inc_return(v)		atomic_add_return(1, (v))

#define atomic_sub_and_test(i,v)	(atomic_sub_return((i), (v)) == 0)
#define atomic_dec_and_test(v)		(atomic_sub_return(1, (v)) == 0)
#define atomic_inc_and_test(v)		(atomic_add_return(1, (v)) == 0)

/*****************************************************************************/
/*
 * exchange value with memory
 */
#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS

#define xchg(ptr, x)								\
({										\
	__typeof__(ptr) __xg_ptr = (ptr);					\
	__typeof__(*(ptr)) __xg_orig;						\
										\
	switch (sizeof(__xg_orig)) {						\
	case 4:									\
		asm volatile(							\
			"swap%I0 %M0,%1"					\
			: "+m"(*__xg_ptr), "=r"(__xg_orig)			\
			: "1"(x)						\
			: "memory"						\
			);							\
		break;								\
										\
	default:								\
		__xg_orig = (__typeof__(__xg_orig))0;				\
		asm volatile("break");						\
		break;								\
	}									\
										\
	__xg_orig;								\
})

#else

extern uint32_t __xchg_32(uint32_t i, volatile void *v);

#define xchg(ptr, x)										\
({												\
	__typeof__(ptr) __xg_ptr = (ptr);							\
	__typeof__(*(ptr)) __xg_orig;								\
												\
	switch (sizeof(__xg_orig)) {								\
	case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr);	break;	\
	default:										\
		__xg_orig = (__typeof__(__xg_orig))0;									\
		asm volatile("break");								\
		break;										\
	}											\
	__xg_orig;										\
})

#endif

#define tas(ptr) (xchg((ptr), 1))

#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
{
	int c, old;
	c = atomic_read(v);
	for (;;) {
		if (unlikely(c == (u)))
			break;
		old = atomic_cmpxchg((v), c, c + (a));
		if (likely(old == c))
			break;
		c = old;
	}
	return c != (u);
}

#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)

#include <asm-generic/atomic.h>
#endif /* _ASM_ATOMIC_H */
Commit	Line	Data
1da177e4 LT	1	/* atomic.h: atomic operation emulation for FR-V
	2	*
	3	* For an explanation of how atomic ops work in this arch, see:
0868ff7a	4	* Documentation/frv/atomic-ops.txt
1da177e4 LT	5	*
	6	* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
	7	* Written by David Howells (dhowells@redhat.com)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14	#ifndef _ASM_ATOMIC_H
	15	#define _ASM_ATOMIC_H
	16
1da177e4 LT	17	#include <linux/types.h>
1da177e4 LT	18	#include <asm/spr-regs.h>
2856f5e3	19	#include <asm/system.h>
1da177e4 LT	20
	21	#ifdef CONFIG_SMP
	22	#error not SMP safe
	23	#endif
	24
	25	/*
	26	* Atomic operations that C can't guarantee us. Useful for
	27	* resource counting etc..
	28	*
	29	* We do not have SMP systems, so we don't have to deal with that.
	30	*/
	31
	32	/* Atomic operations are already serializing */
	33	#define smp_mb__before_atomic_dec() barrier()
	34	#define smp_mb__after_atomic_dec() barrier()
	35	#define smp_mb__before_atomic_inc() barrier()
	36	#define smp_mb__after_atomic_inc() barrier()
	37
1da177e4 LT	38	#define ATOMIC_INIT(i) { (i) }
	39	#define atomic_read(v) ((v)->counter)
	40	#define atomic_set(v, i) (((v)->counter) = (i))
	41
	42	#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
	43	static inline int atomic_add_return(int i, atomic_t *v)
	44	{
	45	unsigned long val;
	46
	47	asm("0: \n"
	48	" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
	49	" ckeq icc3,cc7 \n"
	50	" ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
	51	" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
	52	" add%I2 %1,%2,%1 \n"
	53	" cst.p %1,%M0 ,cc3,#1 \n"
	54	" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
	55	" beq icc3,#0,0b \n"
	56	: "+U"(v->counter), "=&r"(val)
	57	: "NPr"(i)
	58	: "memory", "cc7", "cc3", "icc3"
	59	);
	60
	61	return val;
	62	}
	63
	64	static inline int atomic_sub_return(int i, atomic_t *v)
	65	{
	66	unsigned long val;
	67
	68	asm("0: \n"
	69	" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
	70	" ckeq icc3,cc7 \n"
	71	" ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
	72	" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
	73	" sub%I2 %1,%2,%1 \n"
	74	" cst.p %1,%M0 ,cc3,#1 \n"
	75	" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
	76	" beq icc3,#0,0b \n"
	77	: "+U"(v->counter), "=&r"(val)
	78	: "NPr"(i)
	79	: "memory", "cc7", "cc3", "icc3"
	80	);
	81
	82	return val;
	83	}
	84
	85	#else
	86
	87	extern int atomic_add_return(int i, atomic_t *v);
	88	extern int atomic_sub_return(int i, atomic_t *v);
	89
	90	#endif
	91
	92	static inline int atomic_add_negative(int i, atomic_t *v)
	93	{
	94	return atomic_add_return(i, v) < 0;
	95	}
	96
	97	static inline void atomic_add(int i, atomic_t *v)
	98	{
	99	atomic_add_return(i, v);
	100	}
	101
102	static inline void atomic_sub(int i, atomic_t *v)
103	{
104	atomic_sub_return(i, v);
105	}
106
107	static inline void atomic_inc(atomic_t *v)
108	{
109	atomic_add_return(1, v);
110	}
111
112	static inline void atomic_dec(atomic_t *v)
113	{
114	atomic_sub_return(1, v);
115	}
116
117	#define atomic_dec_return(v) atomic_sub_return(1, (v))
118	#define atomic_inc_return(v) atomic_add_return(1, (v))
119
120	#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
121	#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
122	#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
123
1da177e4 LT	124	/*****************************************************************************/
	125	/*
	126	* exchange value with memory
	127	*/
	128	#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
	129
	130	#define xchg(ptr, x) \
	131	({ \
	132	__typeof__(ptr) __xg_ptr = (ptr); \
	133	__typeof__(*(ptr)) __xg_orig; \
	134	\
	135	switch (sizeof(__xg_orig)) { \
1da177e4 LT	136	case 4: \
1da177e4 LT	137	asm volatile( \
68f624fc DH	138	"swap%I0 %M0,%1" \
	139	: "+m"(*__xg_ptr), "=r"(__xg_orig) \
	140	: "1"(x) \
2fa9e7e2	141	: "memory" \
1da177e4 LT	142	); \
	143	break; \
	144	\
	145	default: \
7f788435	146	__xg_orig = (__typeof__(__xg_orig))0; \
1da177e4 LT	147	asm volatile("break"); \
	148	break; \
	149	} \
	150	\
	151	__xg_orig; \
	152	})
	153
	154	#else
	155
1da177e4 LT	156	extern uint32_t __xchg_32(uint32_t i, volatile void *v);
	157
	158	#define xchg(ptr, x) \
	159	({ \
	160	__typeof__(ptr) __xg_ptr = (ptr); \
	161	__typeof__(*(ptr)) __xg_orig; \
	162	\
	163	switch (sizeof(__xg_orig)) { \
1da177e4 LT	164	case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \
1da177e4 LT	165	default: \
7f788435	166	__xg_orig = (__typeof__(__xg_orig))0; \
1da177e4 LT	167	asm volatile("break"); \
	168	break; \
	169	} \
	170	__xg_orig; \
	171	})
	172
	173	#endif
	174
	175	#define tas(ptr) (xchg((ptr), 1))
	176
2fa9e7e2	177	#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
ffbf670f	178	#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
4a6dae6d	179
2856f5e3 MD	180	static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
	181	{
	182	int c, old;
	183	c = atomic_read(v);
	184	for (;;) {
	185	if (unlikely(c == (u)))
	186	break;
	187	old = atomic_cmpxchg((v), c, c + (a));
	188	if (likely(old == c))
	189	break;
	190	c = old;
	191	}
	192	return c != (u);
	193	}
2fa9e7e2	194
8426e1f6 NP	195	#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
8426e1f6 NP	196
d3cb4871	197	#include <asm-generic/atomic.h>
1da177e4	198	#endif /* _ASM_ATOMIC_H */