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1da177e4 LT |
1 | /* mb93493-regs.h: MB93493 companion chip registers |
2 | * | |
3 | * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #ifndef _ASM_MB93493_REGS_H | |
13 | #define _ASM_MB93493_REGS_H | |
14 | ||
15 | #include <asm/mb-regs.h> | |
16 | #include <asm/mb93493-irqs.h> | |
17 | ||
18 | #define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); }) | |
19 | ||
20 | #define __set_MB93493(X,V) \ | |
21 | do { \ | |
22 | *(volatile unsigned long *)(__region_CS3 + (X)) = (V); mb(); \ | |
23 | } while(0) | |
24 | ||
25 | #define __get_MB93493_STSR(X) __get_MB93493(0x3c0 + (X) * 4) | |
26 | #define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V)) | |
27 | #define MB93493_STSR_EN | |
28 | ||
29 | #define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4) | |
30 | #define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V)) | |
31 | ||
32 | #define __get_MB93493_DQSR(X) __get_MB93493(0x3e0 + (X) * 4) | |
33 | #define __set_MB93493_DQSR(X,V) __set_MB93493(0x3e0 + (X) * 4, (V)) | |
34 | ||
35 | #define __get_MB93493_LBSER() __get_MB93493(0x3f0) | |
36 | #define __set_MB93493_LBSER(V) __set_MB93493(0x3f0, (V)) | |
37 | ||
38 | #define MB93493_LBSER_VDC 0x00010000 | |
39 | #define MB93493_LBSER_VCC 0x00020000 | |
40 | #define MB93493_LBSER_AUDIO 0x00040000 | |
41 | #define MB93493_LBSER_I2C_0 0x00080000 | |
42 | #define MB93493_LBSER_I2C_1 0x00100000 | |
43 | #define MB93493_LBSER_USB 0x00200000 | |
44 | #define MB93493_LBSER_GPIO 0x00800000 | |
45 | #define MB93493_LBSER_PCMCIA 0x01000000 | |
46 | ||
47 | #define __get_MB93493_LBSR() __get_MB93493(0x3fc) | |
48 | #define __set_MB93493_LBSR(V) __set_MB93493(0x3fc, (V)) | |
49 | ||
50 | /* | |
51 | * video display controller | |
52 | */ | |
53 | #define __get_MB93493_VDC(X) __get_MB93493(MB93493_VDC_##X) | |
54 | #define __set_MB93493_VDC(X,V) __set_MB93493(MB93493_VDC_##X, (V)) | |
55 | ||
56 | #define MB93493_VDC_RCURSOR 0x140 /* cursor position */ | |
57 | #define MB93493_VDC_RCT1 0x144 /* cursor colour 1 */ | |
58 | #define MB93493_VDC_RCT2 0x148 /* cursor colour 2 */ | |
59 | #define MB93493_VDC_RHDC 0x150 /* horizontal display period */ | |
60 | #define MB93493_VDC_RH_MARGINS 0x154 /* horizontal margin sizes */ | |
61 | #define MB93493_VDC_RVDC 0x158 /* vertical display period */ | |
62 | #define MB93493_VDC_RV_MARGINS 0x15c /* vertical margin sizes */ | |
63 | #define MB93493_VDC_RC 0x170 /* VDC control */ | |
64 | #define MB93493_VDC_RCLOCK 0x174 /* clock divider, DMA req delay */ | |
65 | #define MB93493_VDC_RBLACK 0x178 /* black insert sizes */ | |
66 | #define MB93493_VDC_RS 0x17c /* VDC status */ | |
67 | ||
68 | #define __addr_MB93493_VDC_BCI(X) ({ (volatile unsigned long *)(__region_CS3 + 0x000 + (X)); }) | |
69 | #define __addr_MB93493_VDC_TPO(X) (__region_CS3 + 0x1c0 + (X)) | |
70 | ||
71 | #define VDC_TPO_WIDTH 32 | |
72 | ||
73 | #define VDC_RC_DSR 0x00000080 /* VDC master reset */ | |
74 | ||
75 | #define VDC_RS_IT 0x00060000 /* interrupt indicators */ | |
76 | #define VDC_RS_IT_UNDERFLOW 0x00040000 /* - underflow event */ | |
77 | #define VDC_RS_IT_VSYNC 0x00020000 /* - VSYNC event */ | |
78 | #define VDC_RS_DFI 0x00010000 /* current interlace field number */ | |
79 | #define VDC_RS_DFI_TOP 0x00000000 /* - top field */ | |
80 | #define VDC_RS_DFI_BOTTOM 0x00010000 /* - bottom field */ | |
81 | #define VDC_RS_DCSR 0x00000010 /* cursor state */ | |
82 | #define VDC_RS_DCM 0x00000003 /* display mode */ | |
83 | #define VDC_RS_DCM_DISABLED 0x00000000 /* - display disabled */ | |
84 | #define VDC_RS_DCM_STOPPED 0x00000001 /* - VDC stopped */ | |
85 | #define VDC_RS_DCM_FREERUNNING 0x00000002 /* - VDC free-running */ | |
86 | #define VDC_RS_DCM_TRANSFERRING 0x00000003 /* - data being transferred to VDC */ | |
87 | ||
88 | /* | |
89 | * video capture controller | |
90 | */ | |
91 | #define __get_MB93493_VCC(X) __get_MB93493(MB93493_VCC_##X) | |
92 | #define __set_MB93493_VCC(X,V) __set_MB93493(MB93493_VCC_##X, (V)) | |
93 | ||
94 | #define MB93493_VCC_RREDUCT 0x104 /* reduction rate */ | |
95 | #define MB93493_VCC_RHY 0x108 /* horizontal brightness filter coefficients */ | |
96 | #define MB93493_VCC_RHC 0x10c /* horizontal colour-difference filter coefficients */ | |
97 | #define MB93493_VCC_RHSIZE 0x110 /* horizontal cycle sizes */ | |
98 | #define MB93493_VCC_RHBC 0x114 /* horizontal back porch size */ | |
99 | #define MB93493_VCC_RVCC 0x118 /* vertical capture period */ | |
100 | #define MB93493_VCC_RVBC 0x11c /* vertical back porch period */ | |
101 | #define MB93493_VCC_RV 0x120 /* vertical filter coefficients */ | |
102 | #define MB93493_VCC_RDTS 0x128 /* DMA transfer size */ | |
103 | #define MB93493_VCC_RDTS_4B 0x01000000 /* 4-byte transfer */ | |
104 | #define MB93493_VCC_RDTS_32B 0x03000000 /* 32-byte transfer */ | |
105 | #define MB93493_VCC_RDTS_SHIFT 24 | |
106 | #define MB93493_VCC_RCC 0x130 /* VCC control */ | |
107 | #define MB93493_VCC_RIS 0x134 /* VCC interrupt status */ | |
108 | ||
109 | #define __addr_MB93493_VCC_TPI(X) (__region_CS3 + 0x180 + (X)) | |
110 | ||
111 | #define VCC_RHSIZE_RHCC 0x000007ff | |
112 | #define VCC_RHSIZE_RHCC_SHIFT 0 | |
113 | #define VCC_RHSIZE_RHTCC 0x0fff0000 | |
114 | #define VCC_RHSIZE_RHTCC_SHIFT 16 | |
115 | ||
116 | #define VCC_RVBC_RVBC 0x00003f00 | |
117 | #define VCC_RVBC_RVBC_SHIFT 8 | |
118 | ||
119 | #define VCC_RREDUCT_RHR 0x07ff0000 | |
120 | #define VCC_RREDUCT_RHR_SHIFT 16 | |
121 | #define VCC_RREDUCT_RVR 0x000007ff | |
122 | #define VCC_RREDUCT_RVR_SHIFT 0 | |
123 | ||
124 | #define VCC_RCC_CE 0x00000001 /* VCC enable */ | |
125 | #define VCC_RCC_CS 0x00000002 /* request video capture start */ | |
126 | #define VCC_RCC_CPF 0x0000000c /* pixel format */ | |
127 | #define VCC_RCC_CPF_YCBCR_16 0x00000000 /* - YCbCr 4:2:2 16-bit format */ | |
128 | #define VCC_RCC_CPF_RGB 0x00000004 /* - RGB 4:4:4 format */ | |
129 | #define VCC_RCC_CPF_YCBCR_24 0x00000008 /* - YCbCr 4:2:2 24-bit format */ | |
130 | #define VCC_RCC_CPF_BT656 0x0000000c /* - ITU R-BT.656 format */ | |
131 | #define VCC_RCC_CPF_SHIFT 2 | |
132 | #define VCC_RCC_CSR 0x00000080 /* request reset */ | |
133 | #define VCC_RCC_HSIP 0x00000100 /* HSYNC polarity */ | |
134 | #define VCC_RCC_HSIP_LOACT 0x00000000 /* - low active */ | |
135 | #define VCC_RCC_HSIP_HIACT 0x00000100 /* - high active */ | |
136 | #define VCC_RCC_VSIP 0x00000200 /* VSYNC polarity */ | |
137 | #define VCC_RCC_VSIP_LOACT 0x00000000 /* - low active */ | |
138 | #define VCC_RCC_VSIP_HIACT 0x00000200 /* - high active */ | |
139 | #define VCC_RCC_CIE 0x00000800 /* interrupt enable */ | |
140 | #define VCC_RCC_CFP 0x00001000 /* RGB pixel packing */ | |
141 | #define VCC_RCC_CFP_4TO3 0x00000000 /* - pack 4 pixels into 3 words */ | |
142 | #define VCC_RCC_CFP_1TO1 0x00001000 /* - pack 1 pixel into 1 words */ | |
143 | #define VCC_RCC_CSM 0x00006000 /* interlace specification */ | |
144 | #define VCC_RCC_CSM_ONEPASS 0x00002000 /* - non-interlaced */ | |
145 | #define VCC_RCC_CSM_INTERLACE 0x00004000 /* - interlaced */ | |
146 | #define VCC_RCC_CSM_SHIFT 13 | |
147 | #define VCC_RCC_ES 0x00008000 /* capture start polarity */ | |
148 | #define VCC_RCC_ES_NEG 0x00000000 /* - negative edge */ | |
149 | #define VCC_RCC_ES_POS 0x00008000 /* - positive edge */ | |
150 | #define VCC_RCC_IFI 0x00080000 /* inferlace field evaluation reverse */ | |
151 | #define VCC_RCC_FDTS 0x00300000 /* interlace field start */ | |
152 | #define VCC_RCC_FDTS_3_8 0x00000000 /* - 3/8 of horizontal entire cycle */ | |
153 | #define VCC_RCC_FDTS_1_4 0x00100000 /* - 1/4 of horizontal entire cycle */ | |
154 | #define VCC_RCC_FDTS_7_16 0x00200000 /* - 7/16 of horizontal entire cycle */ | |
155 | #define VCC_RCC_FDTS_SHIFT 20 | |
156 | #define VCC_RCC_MOV 0x00400000 /* test bit - always set to 1 */ | |
157 | #define VCC_RCC_STP 0x00800000 /* request video capture stop */ | |
158 | #define VCC_RCC_TO 0x01000000 /* input during top-field only */ | |
159 | ||
160 | #define VCC_RIS_VSYNC 0x01000000 /* VSYNC interrupt */ | |
161 | #define VCC_RIS_OV 0x02000000 /* overflow interrupt */ | |
162 | #define VCC_RIS_BOTTOM 0x08000000 /* interlace bottom field */ | |
163 | #define VCC_RIS_STARTED 0x10000000 /* capture started */ | |
164 | ||
165 | /* | |
166 | * I2C | |
167 | */ | |
168 | #define MB93493_I2C_BSR 0x340 /* bus status */ | |
169 | #define MB93493_I2C_BCR 0x344 /* bus control */ | |
170 | #define MB93493_I2C_CCR 0x348 /* clock control */ | |
171 | #define MB93493_I2C_ADR 0x34c /* address */ | |
172 | #define MB93493_I2C_DTR 0x350 /* data */ | |
173 | #define MB93493_I2C_BC2R 0x35c /* bus control 2 */ | |
174 | ||
175 | #define __addr_MB93493_I2C(port,X) (__region_CS3 + MB93493_I2C_##X + ((port)*0x20)) | |
176 | #define __get_MB93493_I2C(port,X) __get_MB93493(MB93493_I2C_##X + ((port)*0x20)) | |
177 | #define __set_MB93493_I2C(port,X,V) __set_MB93493(MB93493_I2C_##X + ((port)*0x20), (V)) | |
178 | ||
179 | #define I2C_BSR_BB (1 << 7) | |
180 | ||
181 | /* | |
182 | * audio controller (I2S) registers | |
183 | */ | |
184 | #define __get_MB93493_I2S(X) __get_MB93493(MB93493_I2S_##X) | |
185 | #define __set_MB93493_I2S(X,V) __set_MB93493(MB93493_I2S_##X, (V)) | |
186 | ||
187 | #define MB93493_I2S_ALDR 0x300 /* L-channel data */ | |
188 | #define MB93493_I2S_ARDR 0x304 /* R-channel data */ | |
189 | #define MB93493_I2S_APDR 0x308 /* 16-bit packed data */ | |
190 | #define MB93493_I2S_AISTR 0x310 /* status */ | |
191 | #define MB93493_I2S_AICR 0x314 /* control */ | |
192 | ||
193 | #define __addr_MB93493_I2S_ALDR(X) (__region_CS3 + MB93493_I2S_ALDR + (X)) | |
194 | #define __addr_MB93493_I2S_ARDR(X) (__region_CS3 + MB93493_I2S_ARDR + (X)) | |
195 | #define __addr_MB93493_I2S_APDR(X) (__region_CS3 + MB93493_I2S_APDR + (X)) | |
196 | #define __addr_MB93493_I2S_ADR(X) (__region_CS3 + 0x320 + (X)) | |
197 | ||
198 | #define I2S_AISTR_OTST 0x00000003 /* status of output data transfer */ | |
199 | #define I2S_AISTR_OTR 0x00000010 /* output transfer request pending */ | |
200 | #define I2S_AISTR_OUR 0x00000020 /* output FIFO underrun detected */ | |
201 | #define I2S_AISTR_OOR 0x00000040 /* output FIFO overrun detected */ | |
202 | #define I2S_AISTR_ODS 0x00000100 /* output DMA transfer size */ | |
203 | #define I2S_AISTR_ODE 0x00000400 /* output DMA transfer request enable */ | |
204 | #define I2S_AISTR_OTRIE 0x00001000 /* output transfer request interrupt enable */ | |
205 | #define I2S_AISTR_OURIE 0x00002000 /* output FIFO underrun interrupt enable */ | |
206 | #define I2S_AISTR_OORIE 0x00004000 /* output FIFO overrun interrupt enable */ | |
207 | #define I2S_AISTR__OUT_MASK 0x00007570 | |
208 | #define I2S_AISTR_ITST 0x00030000 /* status of input data transfer */ | |
209 | #define I2S_AISTR_ITST_SHIFT 16 | |
210 | #define I2S_AISTR_ITR 0x00100000 /* input transfer request pending */ | |
211 | #define I2S_AISTR_IUR 0x00200000 /* input FIFO underrun detected */ | |
212 | #define I2S_AISTR_IOR 0x00400000 /* input FIFO overrun detected */ | |
213 | #define I2S_AISTR_IDS 0x01000000 /* input DMA transfer size */ | |
214 | #define I2S_AISTR_IDE 0x04000000 /* input DMA transfer request enable */ | |
215 | #define I2S_AISTR_ITRIE 0x10000000 /* input transfer request interrupt enable */ | |
216 | #define I2S_AISTR_IURIE 0x20000000 /* input FIFO underrun interrupt enable */ | |
217 | #define I2S_AISTR_IORIE 0x40000000 /* input FIFO overrun interrupt enable */ | |
218 | #define I2S_AISTR__IN_MASK 0x75700000 | |
219 | ||
220 | #define I2S_AICR_MI 0x00000001 /* mono input requested */ | |
221 | #define I2S_AICR_AMI 0x00000002 /* relation between LRCKI/FS1 and SDI */ | |
222 | #define I2S_AICR_LRI 0x00000004 /* function of LRCKI pin */ | |
223 | #define I2S_AICR_SDMI 0x00000070 /* format of input audio data */ | |
224 | #define I2S_AICR_SDMI_SHIFT 4 | |
225 | #define I2S_AICR_CLI 0x00000080 /* input FIFO clearing control */ | |
226 | #define I2S_AICR_IM 0x00000300 /* input state control */ | |
227 | #define I2S_AICR_IM_SHIFT 8 | |
228 | #define I2S_AICR__IN_MASK 0x000003f7 | |
229 | #define I2S_AICR_MO 0x00001000 /* mono output requested */ | |
230 | #define I2S_AICR_AMO 0x00002000 /* relation between LRCKO/FS0 and SDO */ | |
231 | #define I2S_AICR_AMO_SHIFT 13 | |
232 | #define I2S_AICR_LRO 0x00004000 /* function of LRCKO pin */ | |
233 | #define I2S_AICR_SDMO 0x00070000 /* format of output audio data */ | |
234 | #define I2S_AICR_SDMO_SHIFT 16 | |
235 | #define I2S_AICR_CLO 0x00080000 /* output FIFO clearing control */ | |
236 | #define I2S_AICR_OM 0x00100000 /* output state control */ | |
237 | #define I2S_AICR__OUT_MASK 0x001f7000 | |
238 | #define I2S_AICR_DIV 0x03000000 /* frequency division rate */ | |
239 | #define I2S_AICR_DIV_SHIFT 24 | |
240 | #define I2S_AICR_FL 0x20000000 /* frame length */ | |
241 | #define I2S_AICR_FS 0x40000000 /* frame sync method */ | |
242 | #define I2S_AICR_ME 0x80000000 /* master enable */ | |
243 | ||
244 | /* | |
245 | * PCMCIA | |
246 | */ | |
247 | #define __addr_MB93493_PCMCIA(X) ((volatile unsigned long *)(__region_CS5 + (X))) | |
248 | ||
249 | /* | |
250 | * GPIO | |
251 | */ | |
252 | #define __get_MB93493_GPIO_PDR(X) __get_MB93493(0x380 + (X) * 0xc0) | |
253 | #define __set_MB93493_GPIO_PDR(X,V) __set_MB93493(0x380 + (X) * 0xc0, (V)) | |
254 | ||
255 | #define __get_MB93493_GPIO_GPDR(X) __get_MB93493(0x384 + (X) * 0xc0) | |
256 | #define __set_MB93493_GPIO_GPDR(X,V) __set_MB93493(0x384 + (X) * 0xc0, (V)) | |
257 | ||
258 | #define __get_MB93493_GPIO_SIR(X) __get_MB93493(0x388 + (X) * 0xc0) | |
259 | #define __set_MB93493_GPIO_SIR(X,V) __set_MB93493(0x388 + (X) * 0xc0, (V)) | |
260 | ||
261 | #define __get_MB93493_GPIO_SOR(X) __get_MB93493(0x38c + (X) * 0xc0) | |
262 | #define __set_MB93493_GPIO_SOR(X,V) __set_MB93493(0x38c + (X) * 0xc0, (V)) | |
263 | ||
264 | #define __get_MB93493_GPIO_PDSR(X) __get_MB93493(0x390 + (X) * 0xc0) | |
265 | #define __set_MB93493_GPIO_PDSR(X,V) __set_MB93493(0x390 + (X) * 0xc0, (V)) | |
266 | ||
267 | #define __get_MB93493_GPIO_PDCR(X) __get_MB93493(0x394 + (X) * 0xc0) | |
268 | #define __set_MB93493_GPIO_PDCR(X,V) __set_MB93493(0x394 + (X) * 0xc0, (V)) | |
269 | ||
270 | #define __get_MB93493_GPIO_INTST(X) __get_MB93493(0x398 + (X) * 0xc0) | |
271 | #define __set_MB93493_GPIO_INTST(X,V) __set_MB93493(0x398 + (X) * 0xc0, (V)) | |
272 | ||
273 | #define __get_MB93493_GPIO_IEHL(X) __get_MB93493(0x39c + (X) * 0xc0) | |
274 | #define __set_MB93493_GPIO_IEHL(X,V) __set_MB93493(0x39c + (X) * 0xc0, (V)) | |
275 | ||
276 | #define __get_MB93493_GPIO_IELH(X) __get_MB93493(0x3a0 + (X) * 0xc0) | |
277 | #define __set_MB93493_GPIO_IELH(X,V) __set_MB93493(0x3a0 + (X) * 0xc0, (V)) | |
278 | ||
279 | #endif /* _ASM_MB93493_REGS_H */ |