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3f7e212d AB |
1 | /* Generic I/O port emulation, based on MN10300 code |
2 | * | |
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public Licence | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the Licence, or (at your option) any later version. | |
10 | */ | |
11 | #ifndef __ASM_GENERIC_IO_H | |
12 | #define __ASM_GENERIC_IO_H | |
13 | ||
14 | #include <asm/page.h> /* I/O is all done through memory accesses */ | |
15 | #include <asm/cacheflush.h> | |
16 | #include <linux/types.h> | |
17 | ||
18 | #ifdef CONFIG_GENERIC_IOMAP | |
19 | #include <asm-generic/iomap.h> | |
20 | #endif | |
21 | ||
66eab4df MT |
22 | #include <asm-generic/pci_iomap.h> |
23 | ||
35dbc0e0 | 24 | #ifndef mmiowb |
3f7e212d | 25 | #define mmiowb() do {} while (0) |
35dbc0e0 | 26 | #endif |
3f7e212d AB |
27 | |
28 | /*****************************************************************************/ | |
29 | /* | |
30 | * readX/writeX() are used to access memory mapped devices. On some | |
31 | * architectures the memory mapped IO stuff needs to be accessed | |
32 | * differently. On the simple architectures, we just read/write the | |
33 | * memory location directly. | |
34 | */ | |
35dbc0e0 | 35 | #ifndef __raw_readb |
3f7e212d AB |
36 | static inline u8 __raw_readb(const volatile void __iomem *addr) |
37 | { | |
38 | return *(const volatile u8 __force *) addr; | |
39 | } | |
35dbc0e0 | 40 | #endif |
3f7e212d | 41 | |
35dbc0e0 | 42 | #ifndef __raw_readw |
3f7e212d AB |
43 | static inline u16 __raw_readw(const volatile void __iomem *addr) |
44 | { | |
45 | return *(const volatile u16 __force *) addr; | |
46 | } | |
35dbc0e0 | 47 | #endif |
3f7e212d | 48 | |
35dbc0e0 | 49 | #ifndef __raw_readl |
3f7e212d AB |
50 | static inline u32 __raw_readl(const volatile void __iomem *addr) |
51 | { | |
52 | return *(const volatile u32 __force *) addr; | |
53 | } | |
35dbc0e0 | 54 | #endif |
3f7e212d AB |
55 | |
56 | #define readb __raw_readb | |
57 | #define readw(addr) __le16_to_cpu(__raw_readw(addr)) | |
58 | #define readl(addr) __le32_to_cpu(__raw_readl(addr)) | |
59 | ||
35dbc0e0 | 60 | #ifndef __raw_writeb |
3f7e212d AB |
61 | static inline void __raw_writeb(u8 b, volatile void __iomem *addr) |
62 | { | |
63 | *(volatile u8 __force *) addr = b; | |
64 | } | |
35dbc0e0 | 65 | #endif |
3f7e212d | 66 | |
35dbc0e0 | 67 | #ifndef __raw_writew |
3f7e212d AB |
68 | static inline void __raw_writew(u16 b, volatile void __iomem *addr) |
69 | { | |
70 | *(volatile u16 __force *) addr = b; | |
71 | } | |
35dbc0e0 | 72 | #endif |
3f7e212d | 73 | |
35dbc0e0 | 74 | #ifndef __raw_writel |
3f7e212d AB |
75 | static inline void __raw_writel(u32 b, volatile void __iomem *addr) |
76 | { | |
77 | *(volatile u32 __force *) addr = b; | |
78 | } | |
35dbc0e0 | 79 | #endif |
3f7e212d AB |
80 | |
81 | #define writeb __raw_writeb | |
82 | #define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr) | |
83 | #define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr) | |
84 | ||
85 | #ifdef CONFIG_64BIT | |
86 | static inline u64 __raw_readq(const volatile void __iomem *addr) | |
87 | { | |
88 | return *(const volatile u64 __force *) addr; | |
89 | } | |
90 | #define readq(addr) __le64_to_cpu(__raw_readq(addr)) | |
91 | ||
92 | static inline void __raw_writeq(u64 b, volatile void __iomem *addr) | |
93 | { | |
94 | *(volatile u64 __force *) addr = b; | |
95 | } | |
96 | #define writeq(b,addr) __raw_writeq(__cpu_to_le64(b),addr) | |
97 | #endif | |
98 | ||
7dc59bdd G |
99 | #ifndef PCI_IOBASE |
100 | #define PCI_IOBASE ((void __iomem *) 0) | |
101 | #endif | |
102 | ||
3f7e212d AB |
103 | /*****************************************************************************/ |
104 | /* | |
105 | * traditional input/output functions | |
106 | */ | |
107 | ||
108 | static inline u8 inb(unsigned long addr) | |
109 | { | |
7dc59bdd | 110 | return readb(addr + PCI_IOBASE); |
3f7e212d AB |
111 | } |
112 | ||
113 | static inline u16 inw(unsigned long addr) | |
114 | { | |
7dc59bdd | 115 | return readw(addr + PCI_IOBASE); |
3f7e212d AB |
116 | } |
117 | ||
118 | static inline u32 inl(unsigned long addr) | |
119 | { | |
7dc59bdd | 120 | return readl(addr + PCI_IOBASE); |
3f7e212d AB |
121 | } |
122 | ||
123 | static inline void outb(u8 b, unsigned long addr) | |
124 | { | |
7dc59bdd | 125 | writeb(b, addr + PCI_IOBASE); |
3f7e212d AB |
126 | } |
127 | ||
128 | static inline void outw(u16 b, unsigned long addr) | |
129 | { | |
7dc59bdd | 130 | writew(b, addr + PCI_IOBASE); |
3f7e212d AB |
131 | } |
132 | ||
133 | static inline void outl(u32 b, unsigned long addr) | |
134 | { | |
7dc59bdd | 135 | writel(b, addr + PCI_IOBASE); |
3f7e212d AB |
136 | } |
137 | ||
138 | #define inb_p(addr) inb(addr) | |
139 | #define inw_p(addr) inw(addr) | |
140 | #define inl_p(addr) inl(addr) | |
141 | #define outb_p(x, addr) outb((x), (addr)) | |
142 | #define outw_p(x, addr) outw((x), (addr)) | |
143 | #define outl_p(x, addr) outl((x), (addr)) | |
144 | ||
35dbc0e0 | 145 | #ifndef insb |
3f7e212d AB |
146 | static inline void insb(unsigned long addr, void *buffer, int count) |
147 | { | |
148 | if (count) { | |
149 | u8 *buf = buffer; | |
150 | do { | |
151 | u8 x = inb(addr); | |
152 | *buf++ = x; | |
153 | } while (--count); | |
154 | } | |
155 | } | |
35dbc0e0 | 156 | #endif |
3f7e212d | 157 | |
35dbc0e0 | 158 | #ifndef insw |
3f7e212d AB |
159 | static inline void insw(unsigned long addr, void *buffer, int count) |
160 | { | |
161 | if (count) { | |
162 | u16 *buf = buffer; | |
163 | do { | |
164 | u16 x = inw(addr); | |
165 | *buf++ = x; | |
166 | } while (--count); | |
167 | } | |
168 | } | |
35dbc0e0 | 169 | #endif |
3f7e212d | 170 | |
35dbc0e0 | 171 | #ifndef insl |
3f7e212d AB |
172 | static inline void insl(unsigned long addr, void *buffer, int count) |
173 | { | |
174 | if (count) { | |
175 | u32 *buf = buffer; | |
176 | do { | |
177 | u32 x = inl(addr); | |
178 | *buf++ = x; | |
179 | } while (--count); | |
180 | } | |
181 | } | |
35dbc0e0 | 182 | #endif |
3f7e212d | 183 | |
35dbc0e0 | 184 | #ifndef outsb |
3f7e212d AB |
185 | static inline void outsb(unsigned long addr, const void *buffer, int count) |
186 | { | |
187 | if (count) { | |
188 | const u8 *buf = buffer; | |
189 | do { | |
190 | outb(*buf++, addr); | |
191 | } while (--count); | |
192 | } | |
193 | } | |
35dbc0e0 | 194 | #endif |
3f7e212d | 195 | |
35dbc0e0 | 196 | #ifndef outsw |
3f7e212d AB |
197 | static inline void outsw(unsigned long addr, const void *buffer, int count) |
198 | { | |
199 | if (count) { | |
200 | const u16 *buf = buffer; | |
201 | do { | |
202 | outw(*buf++, addr); | |
203 | } while (--count); | |
204 | } | |
205 | } | |
35dbc0e0 | 206 | #endif |
3f7e212d | 207 | |
35dbc0e0 | 208 | #ifndef outsl |
3f7e212d AB |
209 | static inline void outsl(unsigned long addr, const void *buffer, int count) |
210 | { | |
211 | if (count) { | |
212 | const u32 *buf = buffer; | |
213 | do { | |
214 | outl(*buf++, addr); | |
215 | } while (--count); | |
216 | } | |
217 | } | |
35dbc0e0 | 218 | #endif |
3f7e212d | 219 | |
efb2d31c MF |
220 | static inline void readsl(const void __iomem *addr, void *buf, int len) |
221 | { | |
7dc59bdd | 222 | insl(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
223 | } |
224 | ||
225 | static inline void readsw(const void __iomem *addr, void *buf, int len) | |
226 | { | |
7dc59bdd | 227 | insw(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
228 | } |
229 | ||
230 | static inline void readsb(const void __iomem *addr, void *buf, int len) | |
231 | { | |
7dc59bdd | 232 | insb(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
233 | } |
234 | ||
235 | static inline void writesl(const void __iomem *addr, const void *buf, int len) | |
236 | { | |
7dc59bdd | 237 | outsl(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
238 | } |
239 | ||
240 | static inline void writesw(const void __iomem *addr, const void *buf, int len) | |
241 | { | |
7dc59bdd | 242 | outsw(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
243 | } |
244 | ||
245 | static inline void writesb(const void __iomem *addr, const void *buf, int len) | |
246 | { | |
7dc59bdd | 247 | outsb(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
248 | } |
249 | ||
3f7e212d AB |
250 | #ifndef CONFIG_GENERIC_IOMAP |
251 | #define ioread8(addr) readb(addr) | |
252 | #define ioread16(addr) readw(addr) | |
7387be33 | 253 | #define ioread16be(addr) be16_to_cpu(ioread16(addr)) |
3f7e212d | 254 | #define ioread32(addr) readl(addr) |
7387be33 | 255 | #define ioread32be(addr) be32_to_cpu(ioread32(addr)) |
3f7e212d AB |
256 | |
257 | #define iowrite8(v, addr) writeb((v), (addr)) | |
258 | #define iowrite16(v, addr) writew((v), (addr)) | |
7387be33 | 259 | #define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr)) |
3f7e212d | 260 | #define iowrite32(v, addr) writel((v), (addr)) |
7387be33 | 261 | #define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr)) |
3f7e212d AB |
262 | |
263 | #define ioread8_rep(p, dst, count) \ | |
264 | insb((unsigned long) (p), (dst), (count)) | |
265 | #define ioread16_rep(p, dst, count) \ | |
266 | insw((unsigned long) (p), (dst), (count)) | |
267 | #define ioread32_rep(p, dst, count) \ | |
268 | insl((unsigned long) (p), (dst), (count)) | |
269 | ||
270 | #define iowrite8_rep(p, src, count) \ | |
271 | outsb((unsigned long) (p), (src), (count)) | |
272 | #define iowrite16_rep(p, src, count) \ | |
273 | outsw((unsigned long) (p), (src), (count)) | |
274 | #define iowrite32_rep(p, src, count) \ | |
275 | outsl((unsigned long) (p), (src), (count)) | |
276 | #endif /* CONFIG_GENERIC_IOMAP */ | |
277 | ||
7dc59bdd G |
278 | #ifndef IO_SPACE_LIMIT |
279 | #define IO_SPACE_LIMIT 0xffff | |
280 | #endif | |
3f7e212d AB |
281 | |
282 | #ifdef __KERNEL__ | |
283 | ||
284 | #include <linux/vmalloc.h> | |
285 | #define __io_virt(x) ((void __force *) (x)) | |
286 | ||
287 | #ifndef CONFIG_GENERIC_IOMAP | |
3f7e212d | 288 | struct pci_dev; |
3f7e212d AB |
289 | static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) |
290 | { | |
291 | } | |
292 | #endif /* CONFIG_GENERIC_IOMAP */ | |
293 | ||
294 | /* | |
295 | * Change virtual addresses to physical addresses and vv. | |
296 | * These are pretty trivial | |
297 | */ | |
298 | static inline unsigned long virt_to_phys(volatile void *address) | |
299 | { | |
300 | return __pa((unsigned long)address); | |
301 | } | |
302 | ||
303 | static inline void *phys_to_virt(unsigned long address) | |
304 | { | |
305 | return __va(address); | |
306 | } | |
307 | ||
308 | /* | |
309 | * Change "struct page" to physical address. | |
f1ecc698 JB |
310 | * |
311 | * This implementation is for the no-MMU case only... if you have an MMU | |
312 | * you'll need to provide your own definitions. | |
3f7e212d | 313 | */ |
f1ecc698 | 314 | #ifndef CONFIG_MMU |
3f7e212d AB |
315 | static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) |
316 | { | |
317 | return (void __iomem*) (unsigned long)offset; | |
318 | } | |
319 | ||
320 | #define __ioremap(offset, size, flags) ioremap(offset, size) | |
321 | ||
322 | #ifndef ioremap_nocache | |
323 | #define ioremap_nocache ioremap | |
324 | #endif | |
325 | ||
326 | #ifndef ioremap_wc | |
327 | #define ioremap_wc ioremap_nocache | |
328 | #endif | |
329 | ||
e66d3c49 | 330 | static inline void iounmap(void __iomem *addr) |
3f7e212d AB |
331 | { |
332 | } | |
f1ecc698 | 333 | #endif /* CONFIG_MMU */ |
3f7e212d | 334 | |
82ed223c | 335 | #ifdef CONFIG_HAS_IOPORT |
3f7e212d AB |
336 | #ifndef CONFIG_GENERIC_IOMAP |
337 | static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) | |
338 | { | |
339 | return (void __iomem *) port; | |
340 | } | |
341 | ||
342 | static inline void ioport_unmap(void __iomem *p) | |
343 | { | |
344 | } | |
345 | #else /* CONFIG_GENERIC_IOMAP */ | |
346 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | |
347 | extern void ioport_unmap(void __iomem *p); | |
348 | #endif /* CONFIG_GENERIC_IOMAP */ | |
82ed223c | 349 | #endif /* CONFIG_HAS_IOPORT */ |
3f7e212d AB |
350 | |
351 | #define xlate_dev_kmem_ptr(p) p | |
f1ecc698 | 352 | #define xlate_dev_mem_ptr(p) __va(p) |
3f7e212d AB |
353 | |
354 | #ifndef virt_to_bus | |
355 | static inline unsigned long virt_to_bus(volatile void *address) | |
356 | { | |
357 | return ((unsigned long) address); | |
358 | } | |
359 | ||
360 | static inline void *bus_to_virt(unsigned long address) | |
361 | { | |
362 | return (void *) address; | |
363 | } | |
364 | #endif | |
365 | ||
366 | #define memset_io(a, b, c) memset(__io_virt(a), (b), (c)) | |
367 | #define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c)) | |
368 | #define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c)) | |
369 | ||
370 | #endif /* __KERNEL__ */ | |
371 | ||
372 | #endif /* __ASM_GENERIC_IO_H */ |