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1da177e4 LT |
1 | /* |
2 | * cpufeature.h | |
3 | * | |
4 | * Defines x86 CPU feature bits | |
5 | */ | |
6 | ||
7 | #ifndef __ASM_I386_CPUFEATURE_H | |
8 | #define __ASM_I386_CPUFEATURE_H | |
9 | ||
c7f81c94 | 10 | #ifndef __ASSEMBLY__ |
1da177e4 | 11 | #include <linux/bitops.h> |
c7f81c94 AK |
12 | #endif |
13 | #include <asm/required-features.h> | |
1da177e4 | 14 | |
1d67953f | 15 | #define NCAPINTS 8 /* N 32-bit words worth of info */ |
1da177e4 LT |
16 | |
17 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
18 | #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ | |
19 | #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ | |
20 | #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ | |
21 | #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ | |
22 | #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ | |
23 | #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ | |
24 | #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ | |
25 | #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ | |
26 | #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ | |
27 | #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ | |
28 | #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ | |
29 | #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ | |
30 | #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ | |
31 | #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ | |
32 | #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ | |
33 | #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ | |
34 | #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ | |
35 | #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ | |
36 | #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ | |
d7731c0f | 37 | #define X86_FEATURE_DS (0*32+21) /* Debug Store */ |
1da177e4 LT |
38 | #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ |
39 | #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ | |
40 | #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ | |
41 | /* of FPU context), and CR4.OSFXSR available */ | |
42 | #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ | |
43 | #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ | |
44 | #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ | |
45 | #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ | |
46 | #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ | |
47 | #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ | |
48 | ||
49 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
50 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
51 | #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ | |
52 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ | |
53 | #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ | |
54 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ | |
9bccb23d | 55 | #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ |
1da177e4 LT |
56 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ |
57 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ | |
58 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ | |
59 | ||
60 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
61 | #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ | |
62 | #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ | |
63 | #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ | |
64 | ||
65 | /* Other features, Linux-defined mapping, word 3 */ | |
66 | /* This range is used for feature bits which conflict or are synthesized */ | |
67 | #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ | |
68 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
69 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
70 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
71 | /* cpu types for specific tunings: */ | |
72 | #define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */ | |
73 | #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */ | |
74 | #define X86_FEATURE_P3 (3*32+ 6) /* P3 */ | |
75 | #define X86_FEATURE_P4 (3*32+ 7) /* P4 */ | |
39b3a791 | 76 | #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ |
9a0b5817 | 77 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ |
18bd057b | 78 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ |
0080e667 | 79 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
42ed458a | 80 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
538f188e | 81 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
d3f7eae1 | 82 | /* 14 free */ |
3aefbe07 | 83 | #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ |
ec481536 | 84 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ |
1da177e4 LT |
85 | |
86 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
87 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | |
88 | #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ | |
89 | #define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */ | |
90 | #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ | |
91 | #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ | |
92 | #define X86_FEATURE_CID (4*32+10) /* Context ID */ | |
93 | #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ | |
94 | #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ | |
95 | ||
96 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
97 | #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ | |
98 | #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ | |
99 | #define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ | |
100 | #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ | |
224f611c ML |
101 | #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ |
102 | #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ | |
103 | #define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */ | |
104 | #define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */ | |
105 | #define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */ | |
106 | #define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */ | |
1da177e4 LT |
107 | |
108 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
5b7abc6f PA |
109 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ |
110 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | |
1da177e4 | 111 | |
1d67953f VP |
112 | /* |
113 | * Auxiliary flags: Linux defined - For features scattered in various | |
114 | * CPUID levels like 0x6, 0xA etc | |
115 | */ | |
116 | #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ | |
117 | ||
ec481536 PA |
118 | #define cpu_has(c, bit) \ |
119 | (__builtin_constant_p(bit) && \ | |
120 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ | |
121 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ | |
122 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ | |
123 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ | |
124 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ | |
125 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ | |
1d67953f VP |
126 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ |
127 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ | |
ec481536 PA |
128 | ? 1 : \ |
129 | test_bit(bit, (c)->x86_capability)) | |
3671df85 | 130 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
1da177e4 LT |
131 | |
132 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) | |
133 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) | |
134 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) | |
135 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) | |
136 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) | |
137 | #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) | |
138 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) | |
139 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) | |
140 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) | |
141 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) | |
142 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) | |
143 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) | |
144 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) | |
145 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) | |
146 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) | |
147 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) | |
148 | #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) | |
149 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) | |
150 | #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) | |
151 | #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) | |
152 | #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) | |
153 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) | |
154 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) | |
155 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) | |
156 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) | |
224f611c ML |
157 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) |
158 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) | |
159 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) | |
160 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) | |
161 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) | |
162 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) | |
d7731c0f | 163 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
42ed458a | 164 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
3760dd6e | 165 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) |
538f188e | 166 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
1da177e4 LT |
167 | |
168 | #endif /* __ASM_I386_CPUFEATURE_H */ | |
169 | ||
170 | /* | |
171 | * Local Variables: | |
172 | * mode:c | |
173 | * comment-column:42 | |
174 | * End: | |
175 | */ |