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1da177e4 LT |
1 | #ifndef _I386_PGTABLE_3LEVEL_H |
2 | #define _I386_PGTABLE_3LEVEL_H | |
3 | ||
1da177e4 LT |
4 | /* |
5 | * Intel Physical Address Extension (PAE) Mode - three-level page | |
6 | * tables on PPro+ CPUs. | |
7 | * | |
8 | * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> | |
9 | */ | |
10 | ||
11 | #define pte_ERROR(e) \ | |
12 | printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low) | |
13 | #define pmd_ERROR(e) \ | |
14 | printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e)) | |
15 | #define pgd_ERROR(e) \ | |
16 | printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) | |
17 | ||
18 | #define pud_none(pud) 0 | |
19 | #define pud_bad(pud) 0 | |
20 | #define pud_present(pud) 1 | |
21 | ||
22 | /* | |
23 | * Is the pte executable? | |
24 | */ | |
25 | static inline int pte_x(pte_t pte) | |
26 | { | |
27 | return !(pte_val(pte) & _PAGE_NX); | |
28 | } | |
29 | ||
30 | /* | |
31 | * All present user-pages with !NX bit are user-executable: | |
32 | */ | |
33 | static inline int pte_exec(pte_t pte) | |
34 | { | |
35 | return pte_user(pte) && pte_x(pte); | |
36 | } | |
37 | /* | |
38 | * All present pages with !NX bit are kernel-executable: | |
39 | */ | |
40 | static inline int pte_exec_kernel(pte_t pte) | |
41 | { | |
42 | return pte_x(pte); | |
43 | } | |
44 | ||
45 | /* Rules for using set_pte: the pte being assigned *must* be | |
46 | * either not present or in a state where the hardware will | |
47 | * not attempt to update the pte. In places where this is | |
48 | * not possible, use pte_get_and_clear to obtain the old pte | |
49 | * value and then use set_pte to update it. -ben | |
50 | */ | |
3dc494e8 | 51 | static inline void native_set_pte(pte_t *ptep, pte_t pte) |
1da177e4 LT |
52 | { |
53 | ptep->pte_high = pte.pte_high; | |
54 | smp_wmb(); | |
55 | ptep->pte_low = pte.pte_low; | |
56 | } | |
3dc494e8 JF |
57 | static inline void native_set_pte_at(struct mm_struct *mm, unsigned long addr, |
58 | pte_t *ptep , pte_t pte) | |
59 | { | |
60 | native_set_pte(ptep, pte); | |
61 | } | |
1da177e4 | 62 | |
d6d861e3 ZA |
63 | /* |
64 | * Since this is only called on user PTEs, and the page fault handler | |
65 | * must handle the already racy situation of simultaneous page faults, | |
66 | * we are justified in merely clearing the PTE present bit, followed | |
67 | * by a set. The ordering here is important. | |
68 | */ | |
3dc494e8 JF |
69 | static inline void native_set_pte_present(struct mm_struct *mm, unsigned long addr, |
70 | pte_t *ptep, pte_t pte) | |
d6d861e3 ZA |
71 | { |
72 | ptep->pte_low = 0; | |
73 | smp_wmb(); | |
74 | ptep->pte_high = pte.pte_high; | |
75 | smp_wmb(); | |
76 | ptep->pte_low = pte.pte_low; | |
77 | } | |
78 | ||
3dc494e8 JF |
79 | static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) |
80 | { | |
81 | set_64bit((unsigned long long *)(ptep),native_pte_val(pte)); | |
82 | } | |
83 | static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) | |
84 | { | |
85 | set_64bit((unsigned long long *)(pmdp),native_pmd_val(pmd)); | |
86 | } | |
87 | static inline void native_set_pud(pud_t *pudp, pud_t pud) | |
88 | { | |
89 | *pudp = pud; | |
90 | } | |
1da177e4 | 91 | |
6e5882cf ZA |
92 | /* |
93 | * For PTEs and PDEs, we must clear the P-bit first when clearing a page table | |
94 | * entry, so clear the bottom half first and enforce ordering with a compiler | |
95 | * barrier. | |
96 | */ | |
3dc494e8 | 97 | static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
6e5882cf ZA |
98 | { |
99 | ptep->pte_low = 0; | |
100 | smp_wmb(); | |
101 | ptep->pte_high = 0; | |
102 | } | |
103 | ||
3dc494e8 | 104 | static inline void native_pmd_clear(pmd_t *pmd) |
6e5882cf ZA |
105 | { |
106 | u32 *tmp = (u32 *)pmd; | |
107 | *tmp = 0; | |
108 | smp_wmb(); | |
109 | *(tmp + 1) = 0; | |
110 | } | |
3dc494e8 JF |
111 | |
112 | #ifndef CONFIG_PARAVIRT | |
113 | #define set_pte(ptep, pte) native_set_pte(ptep, pte) | |
114 | #define set_pte_at(mm, addr, ptep, pte) native_set_pte_at(mm, addr, ptep, pte) | |
115 | #define set_pte_present(mm, addr, ptep, pte) native_set_pte_present(mm, addr, ptep, pte) | |
116 | #define set_pte_atomic(ptep, pte) native_set_pte_atomic(ptep, pte) | |
117 | #define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd) | |
118 | #define set_pud(pudp, pud) native_set_pud(pudp, pud) | |
119 | #define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep) | |
120 | #define pmd_clear(pmd) native_pmd_clear(pmd) | |
da181a8b RR |
121 | #endif |
122 | ||
123 | /* | |
124 | * Pentium-II erratum A13: in PAE mode we explicitly have to flush | |
125 | * the TLB via cr3 if the top-level pgd is changed... | |
126 | * We do not let the generic code free and clear pgd entries due to | |
127 | * this erratum. | |
128 | */ | |
129 | static inline void pud_clear (pud_t * pud) { } | |
130 | ||
131 | #define pud_page(pud) \ | |
132 | ((struct page *) __va(pud_val(pud) & PAGE_MASK)) | |
133 | ||
134 | #define pud_page_vaddr(pud) \ | |
135 | ((unsigned long) __va(pud_val(pud) & PAGE_MASK)) | |
136 | ||
137 | ||
138 | /* Find an entry in the second-level page table.. */ | |
139 | #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \ | |
140 | pmd_index(address)) | |
6e5882cf | 141 | |
142dd975 | 142 | #ifdef CONFIG_SMP |
3dc494e8 | 143 | static inline pte_t native_ptep_get_and_clear(pte_t *ptep) |
1da177e4 LT |
144 | { |
145 | pte_t res; | |
146 | ||
147 | /* xchg acts as a barrier before the setting of the high bits */ | |
148 | res.pte_low = xchg(&ptep->pte_low, 0); | |
149 | res.pte_high = ptep->pte_high; | |
150 | ptep->pte_high = 0; | |
151 | ||
152 | return res; | |
153 | } | |
142dd975 ZA |
154 | #else |
155 | #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) | |
156 | #endif | |
1da177e4 | 157 | |
6049742d | 158 | #define __HAVE_ARCH_PTE_SAME |
1da177e4 LT |
159 | static inline int pte_same(pte_t a, pte_t b) |
160 | { | |
161 | return a.pte_low == b.pte_low && a.pte_high == b.pte_high; | |
162 | } | |
163 | ||
164 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
165 | ||
166 | static inline int pte_none(pte_t pte) | |
167 | { | |
168 | return !pte.pte_low && !pte.pte_high; | |
169 | } | |
170 | ||
171 | static inline unsigned long pte_pfn(pte_t pte) | |
172 | { | |
3dc494e8 | 173 | return pte_val(pte) >> PAGE_SHIFT; |
1da177e4 LT |
174 | } |
175 | ||
176 | extern unsigned long long __supported_pte_mask; | |
177 | ||
178 | static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) | |
179 | { | |
3dc494e8 JF |
180 | return __pte((((unsigned long long)page_nr << PAGE_SHIFT) | |
181 | pgprot_val(pgprot)) & __supported_pte_mask); | |
1da177e4 LT |
182 | } |
183 | ||
184 | static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) | |
185 | { | |
3dc494e8 JF |
186 | return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | |
187 | pgprot_val(pgprot)) & __supported_pte_mask); | |
1da177e4 LT |
188 | } |
189 | ||
190 | /* | |
191 | * Bits 0, 6 and 7 are taken in the low part of the pte, | |
192 | * put the 32 bits of offset into the high part. | |
193 | */ | |
194 | #define pte_to_pgoff(pte) ((pte).pte_high) | |
195 | #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) }) | |
196 | #define PTE_FILE_MAX_BITS 32 | |
197 | ||
198 | /* Encode and de-code a swap entry */ | |
199 | #define __swp_type(x) (((x).val) & 0x1f) | |
200 | #define __swp_offset(x) ((x).val >> 5) | |
201 | #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5}) | |
202 | #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high }) | |
203 | #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val }) | |
204 | ||
205 | #define __pmd_free_tlb(tlb, x) do { } while (0) | |
206 | ||
207 | #endif /* _I386_PGTABLE_3LEVEL_H */ |