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x86: sanitize pathes arch/x86/kernel/cpu/Makefile
[deliverable/linux.git] / include / asm-i386 / processor.h
CommitLineData
1da177e4
LT		 1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
1da177e4
LT		 20#include <linux/threads.h>
21#include <asm/percpu.h>
1e9f28fa 22#include <linux/cpumask.h>
d7cd5611 23#include <linux/init.h>
b4531e86 24#include <asm/processor-flags.h>
1da177e4
LT		 25
26/* flag for disabling the tsc */
27extern int tsc_disable;
28
29struct desc_struct {
30 unsigned long a,b;
31};
32
33#define desc_empty(desc) \
12aaa085 34 (!((desc)->a | (desc)->b))
1da177e4
LT		 35
36#define desc_equal(desc1, desc2) \
37 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
38/*
39 * Default implementation of macro that returns current
40 * instruction pointer ("program counter").
41 */
42#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43
44/*
45 * CPU type and hardware bug flags. Kept separately for each CPU.
46 * Members of this structure are referenced in head.S, so think twice
47 * before touching them. [mj]
48 */
49
50struct cpuinfo_x86 {
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
53 __u8 x86_model;
54 __u8 x86_mask;
55 char wp_works_ok; /* It doesn't on 386's */
56 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
57 char hard_math;
58 char rfu;
59 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
60 unsigned long x86_capability[NCAPINTS];
61 char x86_vendor_id[16];
62 char x86_model_id[64];
63 int x86_cache_size; /* in KB - valid for CPUS which support this
64 call */
65 int x86_cache_alignment; /* In bytes */
3f98bc49
AK		 66 char fdiv_bug;
67 char f00f_bug;
68 char coma_bug;
69 char pad0;
70 int x86_power;
1da177e4 71 unsigned long loops_per_jiffy;
1e9f28fa
SS		 72#ifdef CONFIG_SMP
73 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
74#endif
94605eff 75 unsigned char x86_max_cores; /* cpuid returned max cores value */
94605eff 76 unsigned char apicid;
770d132f 77 unsigned short x86_clflush_size;
4b89aff9
RS		 78#ifdef CONFIG_SMP
79 unsigned char booted_cores; /* number of cores as seen by OS */
80 __u8 phys_proc_id; /* Physical processor id. */
81 __u8 cpu_core_id; /* Core id */
82#endif
1da177e4
LT		 83} __attribute__((__aligned__(SMP_CACHE_BYTES)));
84
85#define X86_VENDOR_INTEL 0
86#define X86_VENDOR_CYRIX 1
87#define X86_VENDOR_AMD 2
88#define X86_VENDOR_UMC 3
89#define X86_VENDOR_NEXGEN 4
90#define X86_VENDOR_CENTAUR 5
1da177e4
LT		 91#define X86_VENDOR_TRANSMETA 7
92#define X86_VENDOR_NSC 8
93#define X86_VENDOR_NUM 9
94#define X86_VENDOR_UNKNOWN 0xff
95
96/*
97 * capabilities of CPUs
98 */
99
100extern struct cpuinfo_x86 boot_cpu_data;
101extern struct cpuinfo_x86 new_cpu_data;
102extern struct tss_struct doublefault_tss;
103DECLARE_PER_CPU(struct tss_struct, init_tss);
104
105#ifdef CONFIG_SMP
106extern struct cpuinfo_x86 cpu_data[];
107#define current_cpu_data cpu_data[smp_processor_id()]
108#else
109#define cpu_data (&boot_cpu_data)
110#define current_cpu_data boot_cpu_data
111#endif
112
1e9f28fa 113extern int cpu_llc_id[NR_CPUS];
1da177e4
LT		 114extern char ignore_fpu_irq;
115
d7cd5611
RR		 116void __init cpu_detect(struct cpuinfo_x86 *c);
117
a6c4e076
JF		 118extern void identify_boot_cpu(void);
119extern void identify_secondary_cpu(struct cpuinfo_x86 *);
1da177e4 120extern void print_cpu_info(struct cpuinfo_x86 *);
1d67953f 121extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
1da177e4 122extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
240cd6a8 123extern unsigned short num_cache_leaves;
1da177e4
LT		 124
125#ifdef CONFIG_X86_HT
126extern void detect_ht(struct cpuinfo_x86 *c);
127#else
128static inline void detect_ht(struct cpuinfo_x86 *c) {}
129#endif
130
90a0a06a 131static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
d3561b7f 132 unsigned int *ecx, unsigned int *edx)
9f093394
RR		 133{
134 /* ecx is often an input as well as an output. */
135 __asm__("cpuid"
136 : "=a" (*eax),
137 "=b" (*ebx),
138 "=c" (*ecx),
139 "=d" (*edx)
140 : "0" (*eax), "2" (*ecx));
141}
142
4bb0d3ec 143#define load_cr3(pgdir) write_cr3(__pa(pgdir))
1da177e4 144
1da177e4
LT		 145/*
146 * Save the cr4 feature set we're using (ie
147 * Pentium 4MB enable and PPro Global page
148 * enable), so that any CPU's that boot up
149 * after us can get the correct flags.
150 */
151extern unsigned long mmu_cr4_features;
152
153static inline void set_in_cr4 (unsigned long mask)
154{
4bb0d3ec 155 unsigned cr4;
1da177e4 156 mmu_cr4_features |= mask;
4bb0d3ec
ZA		 157 cr4 = read_cr4();
158 cr4 |= mask;
159 write_cr4(cr4);
1da177e4
LT		 160}
161
162static inline void clear_in_cr4 (unsigned long mask)
163{
4bb0d3ec 164 unsigned cr4;
1da177e4 165 mmu_cr4_features &= ~mask;
4bb0d3ec
ZA		 166 cr4 = read_cr4();
167 cr4 &= ~mask;
168 write_cr4(cr4);
1da177e4
LT		 169}
170
487472bc
AK		 171/* Stop speculative execution */
172static inline void sync_core(void)
245067d1 173{
487472bc
AK		 174 int tmp;
175 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
245067d1
ZA		 176}
177
1da177e4
LT		 178static inline void __monitor(const void *eax, unsigned long ecx,
179 unsigned long edx)
180{
181 /* "monitor %eax,%ecx,%edx;" */
182 asm volatile(
183 ".byte 0x0f,0x01,0xc8;"
184 : :"a" (eax), "c" (ecx), "d"(edx));
185}
186
187static inline void __mwait(unsigned long eax, unsigned long ecx)
188{
189 /* "mwait %eax,%ecx;" */
190 asm volatile(
191 ".byte 0x0f,0x01,0xc9;"
192 : :"a" (eax), "c" (ecx));
193}
194
991528d7
VP		 195extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
196
1da177e4
LT		 197/* from system description table in BIOS. Mostly for MCA use, but
198others may find it useful. */
199extern unsigned int machine_id;
200extern unsigned int machine_submodel_id;
201extern unsigned int BIOS_revision;
202extern unsigned int mca_pentium_flag;
203
204/* Boot loader type from the setup header */
205extern int bootloader_type;
206
207/*
208 * User space process size: 3GB (default).
209 */
210#define TASK_SIZE (PAGE_OFFSET)
211
212/* This decides where the kernel will search for a free chunk of vm
213 * space during mmap's.
214 */
215#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
216
217#define HAVE_ARCH_PICK_MMAP_LAYOUT
218
cf99abac
AA		 219extern void hard_disable_TSC(void);
220extern void disable_TSC(void);
221extern void hard_enable_TSC(void);
222
1da177e4
LT		 223/*
224 * Size of io_bitmap.
225 */
226#define IO_BITMAP_BITS 65536
227#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
228#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
229#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
230#define INVALID_IO_BITMAP_OFFSET 0x8000
231#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
232
233struct i387_fsave_struct {
234 long cwd;
235 long swd;
236 long twd;
237 long fip;
238 long fcs;
239 long foo;
240 long fos;
241 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
242 long status; /* software status information */
243};
244
245struct i387_fxsave_struct {
246 unsigned short cwd;
247 unsigned short swd;
248 unsigned short twd;
249 unsigned short fop;
250 long fip;
251 long fcs;
252 long foo;
253 long fos;
254 long mxcsr;
255 long mxcsr_mask;
256 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
257 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
258 long padding[56];
259} __attribute__ ((aligned (16)));
260
261struct i387_soft_struct {
262 long cwd;
263 long swd;
264 long twd;
265 long fip;
266 long fcs;
267 long foo;
268 long fos;
269 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
270 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
271 struct info *info;
272 unsigned long entry_eip;
273};
274
275union i387_union {
276 struct i387_fsave_struct fsave;
277 struct i387_fxsave_struct fxsave;
278 struct i387_soft_struct soft;
279};
280
281typedef struct {
282 unsigned long seg;
283} mm_segment_t;
284
285struct thread_struct;
286
a75c54f9
RR		 287/* This is the TSS defined by the hardware. */
288struct i386_hw_tss {
1da177e4
LT		 289 unsigned short back_link,__blh;
290 unsigned long esp0;
291 unsigned short ss0,__ss0h;
292 unsigned long esp1;
293 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
294 unsigned long esp2;
295 unsigned short ss2,__ss2h;
296 unsigned long __cr3;
297 unsigned long eip;
298 unsigned long eflags;
299 unsigned long eax,ecx,edx,ebx;
300 unsigned long esp;
301 unsigned long ebp;
302 unsigned long esi;
303 unsigned long edi;
304 unsigned short es, __esh;
305 unsigned short cs, __csh;
306 unsigned short ss, __ssh;
307 unsigned short ds, __dsh;
308 unsigned short fs, __fsh;
309 unsigned short gs, __gsh;
310 unsigned short ldt, __ldth;
311 unsigned short trace, io_bitmap_base;
a75c54f9
RR		 312} __attribute__((packed));
313
314struct tss_struct {
315 struct i386_hw_tss x86_tss;
316
1da177e4
LT		 317 /*
318 * The extra 1 is there because the CPU will access an
319 * additional byte beyond the end of the IO permission
320 * bitmap. The extra byte must be all 1 bits, and must
321 * be within the limit.
322 */
323 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
324 /*
325 * Cache the current maximum and the last task that used the bitmap:
326 */
327 unsigned long io_bitmap_max;
328 struct thread_struct *io_bitmap_owner;
329 /*
330 * pads the TSS to be cacheline-aligned (size is 0x100)
331 */
332 unsigned long __cacheline_filler[35];
333 /*
334 * .. and then another 0x100 bytes for emergency kernel stack
335 */
336 unsigned long stack[64];
337} __attribute__((packed));
338
339#define ARCH_MIN_TASKALIGN 16
340
341struct thread_struct {
342/* cached TLS descriptors. */
343 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
344 unsigned long esp0;
345 unsigned long sysenter_cs;
346 unsigned long eip;
347 unsigned long esp;
348 unsigned long fs;
349 unsigned long gs;
350/* Hardware debugging registers */
351 unsigned long debugreg[8]; /* %%db0-7 debug registers */
352/* fault info */
353 unsigned long cr2, trap_no, error_code;
354/* floating point info */
355 union i387_union i387;
356/* virtual 86 mode info */
357 struct vm86_struct __user * vm86_info;
358 unsigned long screen_bitmap;
359 unsigned long v86flags, v86mask, saved_esp0;
360 unsigned int saved_fs, saved_gs;
361/* IO permissions */
362 unsigned long *io_bitmap_ptr;
a5201129 363 unsigned long iopl;
1da177e4
LT		 364/* max allowed port in the bitmap, in bytes: */
365 unsigned long io_bitmap_max;
366};
367
368#define INIT_THREAD { \
692174b9 369 .esp0 = sizeof(init_stack) + (long)&init_stack, \
1da177e4
LT		 370 .vm86_info = NULL, \
371 .sysenter_cs = __KERNEL_CS, \
372 .io_bitmap_ptr = NULL, \
7c3576d2 373 .fs = __KERNEL_PERCPU, \
1da177e4
LT		 374}
375
376/*
377 * Note that the .io_bitmap member must be extra-big. This is because
378 * the CPU will access an additional byte beyond the end of the IO
379 * permission bitmap. The extra byte must be all 1 bits, and must
380 * be within the limit.
381 */
382#define INIT_TSS { \
a75c54f9
RR		 383 .x86_tss = { \
384 .esp0 = sizeof(init_stack) + (long)&init_stack, \
385 .ss0 = __KERNEL_DS, \
386 .ss1 = __KERNEL_CS, \
387 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
388 }, \
1da177e4
LT		 389 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
390}
391
1da177e4 392#define start_thread(regs, new_eip, new_esp) do { \
464d1a78
JF		 393 __asm__("movl %0,%%gs": :"r" (0)); \
394 regs->xfs = 0; \
1da177e4
LT		 395 set_fs(USER_DS); \
396 regs->xds = __USER_DS; \
397 regs->xes = __USER_DS; \
398 regs->xss = __USER_DS; \
399 regs->xcs = __USER_CS; \
400 regs->eip = new_eip; \
401 regs->esp = new_esp; \
402} while (0)
403
404/* Forward declaration, a strange C thing */
405struct task_struct;
406struct mm_struct;
407
408/* Free all resources held by a thread. */
409extern void release_thread(struct task_struct *);
410
411/* Prepare to copy thread state - unlazy all lazy status */
412extern void prepare_to_copy(struct task_struct *tsk);
413
414/*
415 * create a kernel thread without removing it from tasklists
416 */
417extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
418
419extern unsigned long thread_saved_pc(struct task_struct *tsk);
176a2718 420void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
1da177e4
LT		 421
422unsigned long get_wchan(struct task_struct *p);
423
424#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
425#define KSTK_TOP(info) \
426({ \
427 unsigned long *__ptr = (unsigned long *)(info); \
428 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
429})
430
07b047fc 431/*
432 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
433 * This is necessary to guarantee that the entire "struct pt_regs"
434 * is accessable even if the CPU haven't stored the SS/ESP registers
435 * on the stack (interrupt gate does not save these registers
436 * when switching to the same priv ring).
437 * Therefore beware: accessing the xss/esp fields of the
438 * "struct pt_regs" is possible, but they may contain the
439 * completely wrong values.
440 */
1da177e4
LT		 441#define task_pt_regs(task) \
442({ \
443 struct pt_regs *__regs__; \
65e0fdff 444 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
1da177e4
LT		 445 __regs__ - 1; \
446})
447
448#define KSTK_EIP(task) (task_pt_regs(task)->eip)
449#define KSTK_ESP(task) (task_pt_regs(task)->esp)
450
451
452struct microcode_header {
453 unsigned int hdrver;
454 unsigned int rev;
455 unsigned int date;
456 unsigned int sig;
457 unsigned int cksum;
458 unsigned int ldrver;
459 unsigned int pf;
460 unsigned int datasize;
461 unsigned int totalsize;
462 unsigned int reserved[3];
463};
464
465struct microcode {
466 struct microcode_header hdr;
467 unsigned int bits[0];
468};
469
470typedef struct microcode microcode_t;
471typedef struct microcode_header microcode_header_t;
472
473/* microcode format is extended from prescott processors */
474struct extended_signature {
475 unsigned int sig;
476 unsigned int pf;
477 unsigned int cksum;
478};
479
480struct extended_sigtable {
481 unsigned int count;
482 unsigned int cksum;
483 unsigned int reserved[3];
484 struct extended_signature sigs[0];
485};
1da177e4
LT		 486
487/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
488static inline void rep_nop(void)
489{
490 __asm__ __volatile__("rep;nop": : :"memory");
491}
492
493#define cpu_relax() rep_nop()
494
90a0a06a 495static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
139ec7c4 496{
a75c54f9 497 tss->x86_tss.esp0 = thread->esp0;
139ec7c4 498 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
a75c54f9
RR		 499 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
500 tss->x86_tss.ss1 = thread->sysenter_cs;
139ec7c4
RR		 501 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
502 }
503}
504
139ec7c4 505
90a0a06a
RR		 506static inline unsigned long native_get_debugreg(int regno)
507{
508 unsigned long val = 0; /* Damn you, gcc! */
509
510 switch (regno) {
511 case 0:
512 asm("movl %%db0, %0" :"=r" (val)); break;
513 case 1:
514 asm("movl %%db1, %0" :"=r" (val)); break;
515 case 2:
516 asm("movl %%db2, %0" :"=r" (val)); break;
517 case 3:
518 asm("movl %%db3, %0" :"=r" (val)); break;
519 case 6:
520 asm("movl %%db6, %0" :"=r" (val)); break;
521 case 7:
522 asm("movl %%db7, %0" :"=r" (val)); break;
523 default:
524 BUG();
525 }
526 return val;
527}
528
529static inline void native_set_debugreg(int regno, unsigned long value)
530{
531 switch (regno) {
532 case 0:
533 asm("movl %0,%%db0" : /* no output */ :"r" (value));
534 break;
535 case 1:
536 asm("movl %0,%%db1" : /* no output */ :"r" (value));
537 break;
538 case 2:
539 asm("movl %0,%%db2" : /* no output */ :"r" (value));
540 break;
541 case 3:
542 asm("movl %0,%%db3" : /* no output */ :"r" (value));
543 break;
544 case 6:
545 asm("movl %0,%%db6" : /* no output */ :"r" (value));
546 break;
547 case 7:
548 asm("movl %0,%%db7" : /* no output */ :"r" (value));
549 break;
550 default:
551 BUG();
552 }
553}
139ec7c4
RR		 554
555/*
556 * Set IOPL bits in EFLAGS from given mask
557 */
90a0a06a 558static inline void native_set_iopl_mask(unsigned mask)
139ec7c4
RR		 559{
560 unsigned int reg;
561 __asm__ __volatile__ ("pushfl;"
562 "popl %0;"
563 "andl %1, %0;"
564 "orl %2, %0;"
565 "pushl %0;"
566 "popfl"
567 : "=&r" (reg)
568 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
569}
570
90a0a06a
RR		 571#ifdef CONFIG_PARAVIRT
572#include <asm/paravirt.h>
573#else
574#define paravirt_enabled() 0
575#define __cpuid native_cpuid
576
577static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
578{
579 native_load_esp0(tss, thread);
580}
581
582/*
583 * These special macros can be used to get or set a debugging register
584 */
585#define get_debugreg(var, register) \
586 (var) = native_get_debugreg(register)
587#define set_debugreg(value, register) \
588 native_set_debugreg(register, value)
589
590#define set_iopl_mask native_set_iopl_mask
591#endif /* CONFIG_PARAVIRT */
592
139ec7c4
RR		 593/*
594 * Generic CPUID function
595 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
596 * resulting in stale register contents being returned.
597 */
598static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
599{
600 *eax = op;
601 *ecx = 0;
602 __cpuid(eax, ebx, ecx, edx);
603}
604
605/* Some CPUID calls want 'count' to be placed in ecx */
606static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
607 int *edx)
608{
609 *eax = op;
610 *ecx = count;
611 __cpuid(eax, ebx, ecx, edx);
612}
613
614/*
615 * CPUID functions returning a single datum
616 */
617static inline unsigned int cpuid_eax(unsigned int op)
618{
619 unsigned int eax, ebx, ecx, edx;
620
621 cpuid(op, &eax, &ebx, &ecx, &edx);
622 return eax;
623}
624static inline unsigned int cpuid_ebx(unsigned int op)
625{
626 unsigned int eax, ebx, ecx, edx;
627
628 cpuid(op, &eax, &ebx, &ecx, &edx);
629 return ebx;
630}
631static inline unsigned int cpuid_ecx(unsigned int op)
632{
633 unsigned int eax, ebx, ecx, edx;
634
635 cpuid(op, &eax, &ebx, &ecx, &edx);
636 return ecx;
637}
638static inline unsigned int cpuid_edx(unsigned int op)
639{
640 unsigned int eax, ebx, ecx, edx;
641
642 cpuid(op, &eax, &ebx, &ecx, &edx);
643 return edx;
644}
645
1da177e4
LT		 646/* generic versions from gas */
647#define GENERIC_NOP1 ".byte 0x90\n"
648#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
649#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
650#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
651#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
652#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
653#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
654#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
655
656/* Opteron nops */
657#define K8_NOP1 GENERIC_NOP1
658#define K8_NOP2 ".byte 0x66,0x90\n"
659#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
660#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
661#define K8_NOP5 K8_NOP3 K8_NOP2
662#define K8_NOP6 K8_NOP3 K8_NOP3
663#define K8_NOP7 K8_NOP4 K8_NOP3
664#define K8_NOP8 K8_NOP4 K8_NOP4
665
666/* K7 nops */
667/* uses eax dependencies (arbitary choice) */
668#define K7_NOP1 GENERIC_NOP1
669#define K7_NOP2 ".byte 0x8b,0xc0\n"
670#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
671#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
672#define K7_NOP5 K7_NOP4 ASM_NOP1
673#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
674#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
675#define K7_NOP8 K7_NOP7 ASM_NOP1
676
677#ifdef CONFIG_MK8
678#define ASM_NOP1 K8_NOP1
679#define ASM_NOP2 K8_NOP2
680#define ASM_NOP3 K8_NOP3
681#define ASM_NOP4 K8_NOP4
682#define ASM_NOP5 K8_NOP5
683#define ASM_NOP6 K8_NOP6
684#define ASM_NOP7 K8_NOP7
685#define ASM_NOP8 K8_NOP8
686#elif defined(CONFIG_MK7)
687#define ASM_NOP1 K7_NOP1
688#define ASM_NOP2 K7_NOP2
689#define ASM_NOP3 K7_NOP3
690#define ASM_NOP4 K7_NOP4
691#define ASM_NOP5 K7_NOP5
692#define ASM_NOP6 K7_NOP6
693#define ASM_NOP7 K7_NOP7
694#define ASM_NOP8 K7_NOP8
695#else
696#define ASM_NOP1 GENERIC_NOP1
697#define ASM_NOP2 GENERIC_NOP2
698#define ASM_NOP3 GENERIC_NOP3
699#define ASM_NOP4 GENERIC_NOP4
700#define ASM_NOP5 GENERIC_NOP5
701#define ASM_NOP6 GENERIC_NOP6
702#define ASM_NOP7 GENERIC_NOP7
703#define ASM_NOP8 GENERIC_NOP8
704#endif
705
706#define ASM_NOP_MAX 8
707
708/* Prefetch instructions for Pentium III and AMD Athlon */
709/* It's not worth to care about 3dnow! prefetches for the K6
710 because they are microcoded there and very slow.
711 However we don't do prefetches for pre XP Athlons currently
712 That should be fixed. */
713#define ARCH_HAS_PREFETCH
e2afe674 714static inline void prefetch(const void *x)
1da177e4
LT		 715{
716 alternative_input(ASM_NOP4,
717 "prefetchnta (%1)",
718 X86_FEATURE_XMM,
719 "r" (x));
720}
721
722#define ARCH_HAS_PREFETCH
723#define ARCH_HAS_PREFETCHW
724#define ARCH_HAS_SPINLOCK_PREFETCH
725
726/* 3dnow! prefetch to get an exclusive cache line. Useful for
727 spinlocks to avoid one state transition in the cache coherency protocol. */
e2afe674 728static inline void prefetchw(const void *x)
1da177e4
LT		 729{
730 alternative_input(ASM_NOP4,
731 "prefetchw (%1)",
732 X86_FEATURE_3DNOW,
733 "r" (x));
734}
735#define spin_lock_prefetch(x) prefetchw(x)
736
737extern void select_idle_routine(const struct cpuinfo_x86 *c);
738
739#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
740
741extern unsigned long boot_option_idle_override;
6fe940d6
LS		 742extern void enable_sep_cpu(void);
743extern int sysenter_setup(void);
1da177e4 744
297d9c03
JF		 745/* Defined in head.S */
746extern struct Xgt_desc_struct early_gdt_descr;
747
9ee79a3d 748extern void cpu_set_gdt(int);
c5413fbe 749extern void switch_to_new_gdt(void);
d2cbcc49 750extern void cpu_init(void);
297d9c03 751extern void init_gdt(int cpu);
62111195 752
f039b754
AK		 753extern int force_mwait;
754
1da177e4 755#endif /* __ASM_I386_PROCESSOR_H */
Linux kernel - Deliverables
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