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1da177e4 LT |
1 | #ifndef __ASM_SPINLOCK_H |
2 | #define __ASM_SPINLOCK_H | |
3 | ||
4 | #include <asm/atomic.h> | |
5 | #include <asm/rwlock.h> | |
6 | #include <asm/page.h> | |
1da177e4 LT |
7 | #include <linux/compiler.h> |
8 | ||
1da177e4 LT |
9 | /* |
10 | * Your basic SMP spinlocks, allowing only a single CPU anywhere | |
fb1c8f93 | 11 | * |
1da177e4 LT |
12 | * Simple spin lock operations. There are two variants, one clears IRQ's |
13 | * on the local processor, one does not. | |
14 | * | |
15 | * We make no fairness assumptions. They have a cost. | |
fb1c8f93 IM |
16 | * |
17 | * (the type definitions are in asm/spinlock_types.h) | |
1da177e4 LT |
18 | */ |
19 | ||
fb1c8f93 IM |
20 | #define __raw_spin_is_locked(x) \ |
21 | (*(volatile signed char *)(&(x)->slock) <= 0) | |
1da177e4 | 22 | |
fb1c8f93 | 23 | #define __raw_spin_lock_string \ |
1da177e4 LT |
24 | "\n1:\t" \ |
25 | "lock ; decb %0\n\t" \ | |
26 | "jns 3f\n" \ | |
27 | "2:\t" \ | |
28 | "rep;nop\n\t" \ | |
29 | "cmpb $0,%0\n\t" \ | |
30 | "jle 2b\n\t" \ | |
31 | "jmp 1b\n" \ | |
32 | "3:\n\t" | |
33 | ||
fb1c8f93 | 34 | #define __raw_spin_lock_string_flags \ |
1da177e4 LT |
35 | "\n1:\t" \ |
36 | "lock ; decb %0\n\t" \ | |
42c059e0 | 37 | "jns 5f\n" \ |
1da177e4 LT |
38 | "2:\t" \ |
39 | "testl $0x200, %1\n\t" \ | |
42c059e0 CE |
40 | "jz 4f\n\t" \ |
41 | "sti\n" \ | |
1da177e4 LT |
42 | "3:\t" \ |
43 | "rep;nop\n\t" \ | |
44 | "cmpb $0, %0\n\t" \ | |
45 | "jle 3b\n\t" \ | |
46 | "cli\n\t" \ | |
47 | "jmp 1b\n" \ | |
42c059e0 CE |
48 | "4:\t" \ |
49 | "rep;nop\n\t" \ | |
50 | "cmpb $0, %0\n\t" \ | |
51 | "jg 1b\n\t" \ | |
52 | "jmp 4b\n" \ | |
53 | "5:\n\t" | |
1da177e4 | 54 | |
9a0b5817 GH |
55 | #define __raw_spin_lock_string_up \ |
56 | "\n\tdecb %0" | |
57 | ||
fb1c8f93 IM |
58 | static inline void __raw_spin_lock(raw_spinlock_t *lock) |
59 | { | |
9a0b5817 GH |
60 | alternative_smp( |
61 | __raw_spin_lock_string, | |
62 | __raw_spin_lock_string_up, | |
63 | "=m" (lock->slock) : : "memory"); | |
fb1c8f93 IM |
64 | } |
65 | ||
66 | static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) | |
67 | { | |
9a0b5817 GH |
68 | alternative_smp( |
69 | __raw_spin_lock_string_flags, | |
70 | __raw_spin_lock_string_up, | |
71 | "=m" (lock->slock) : "r" (flags) : "memory"); | |
fb1c8f93 IM |
72 | } |
73 | ||
74 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) | |
75 | { | |
76 | char oldval; | |
77 | __asm__ __volatile__( | |
78 | "xchgb %b0,%1" | |
79 | :"=q" (oldval), "=m" (lock->slock) | |
80 | :"0" (0) : "memory"); | |
81 | return oldval > 0; | |
82 | } | |
83 | ||
1da177e4 | 84 | /* |
fb1c8f93 IM |
85 | * __raw_spin_unlock based on writing $1 to the low byte. |
86 | * This method works. Despite all the confusion. | |
87 | * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there) | |
1da177e4 LT |
88 | * (PPro errata 66, 92) |
89 | */ | |
90 | ||
91 | #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE) | |
92 | ||
fb1c8f93 | 93 | #define __raw_spin_unlock_string \ |
1da177e4 LT |
94 | "movb $1,%0" \ |
95 | :"=m" (lock->slock) : : "memory" | |
96 | ||
97 | ||
fb1c8f93 | 98 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) |
1da177e4 | 99 | { |
1da177e4 | 100 | __asm__ __volatile__( |
fb1c8f93 | 101 | __raw_spin_unlock_string |
1da177e4 LT |
102 | ); |
103 | } | |
104 | ||
105 | #else | |
106 | ||
fb1c8f93 | 107 | #define __raw_spin_unlock_string \ |
1da177e4 LT |
108 | "xchgb %b0, %1" \ |
109 | :"=q" (oldval), "=m" (lock->slock) \ | |
110 | :"0" (oldval) : "memory" | |
111 | ||
fb1c8f93 | 112 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) |
1da177e4 LT |
113 | { |
114 | char oldval = 1; | |
1da177e4 | 115 | |
1da177e4 | 116 | __asm__ __volatile__( |
fb1c8f93 IM |
117 | __raw_spin_unlock_string |
118 | ); | |
1da177e4 LT |
119 | } |
120 | ||
1da177e4 | 121 | #endif |
1da177e4 | 122 | |
fb1c8f93 IM |
123 | #define __raw_spin_unlock_wait(lock) \ |
124 | do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) | |
1da177e4 LT |
125 | |
126 | /* | |
127 | * Read-write spinlocks, allowing multiple readers | |
128 | * but only one writer. | |
129 | * | |
130 | * NOTE! it is quite common to have readers in interrupts | |
131 | * but no interrupt writers. For those circumstances we | |
132 | * can "mix" irq-safe locks - any writer needs to get a | |
133 | * irq-safe write-lock, but readers can get non-irqsafe | |
134 | * read-locks. | |
fb1c8f93 IM |
135 | * |
136 | * On x86, we implement read-write locks as a 32-bit counter | |
137 | * with the high bit (sign) being the "contended" bit. | |
138 | * | |
139 | * The inline assembly is non-obvious. Think about it. | |
140 | * | |
141 | * Changed to use the same technique as rw semaphores. See | |
142 | * semaphore.h for details. -ben | |
143 | * | |
144 | * the helpers are in arch/i386/kernel/semaphore.c | |
1da177e4 | 145 | */ |
1da177e4 LT |
146 | |
147 | /** | |
148 | * read_can_lock - would read_trylock() succeed? | |
149 | * @lock: the rwlock in question. | |
150 | */ | |
fb1c8f93 | 151 | #define __raw_read_can_lock(x) ((int)(x)->lock > 0) |
1da177e4 LT |
152 | |
153 | /** | |
154 | * write_can_lock - would write_trylock() succeed? | |
155 | * @lock: the rwlock in question. | |
156 | */ | |
fb1c8f93 | 157 | #define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS) |
1da177e4 | 158 | |
fb1c8f93 | 159 | static inline void __raw_read_lock(raw_rwlock_t *rw) |
1da177e4 | 160 | { |
1da177e4 LT |
161 | __build_read_lock(rw, "__read_lock_failed"); |
162 | } | |
163 | ||
fb1c8f93 | 164 | static inline void __raw_write_lock(raw_rwlock_t *rw) |
1da177e4 | 165 | { |
1da177e4 LT |
166 | __build_write_lock(rw, "__write_lock_failed"); |
167 | } | |
168 | ||
fb1c8f93 | 169 | static inline int __raw_read_trylock(raw_rwlock_t *lock) |
1da177e4 LT |
170 | { |
171 | atomic_t *count = (atomic_t *)lock; | |
172 | atomic_dec(count); | |
173 | if (atomic_read(count) >= 0) | |
174 | return 1; | |
175 | atomic_inc(count); | |
176 | return 0; | |
177 | } | |
178 | ||
fb1c8f93 | 179 | static inline int __raw_write_trylock(raw_rwlock_t *lock) |
1da177e4 LT |
180 | { |
181 | atomic_t *count = (atomic_t *)lock; | |
182 | if (atomic_sub_and_test(RW_LOCK_BIAS, count)) | |
183 | return 1; | |
184 | atomic_add(RW_LOCK_BIAS, count); | |
185 | return 0; | |
186 | } | |
187 | ||
fb1c8f93 IM |
188 | static inline void __raw_read_unlock(raw_rwlock_t *rw) |
189 | { | |
9a0b5817 | 190 | asm volatile(LOCK_PREFIX "incl %0" :"=m" (rw->lock) : : "memory"); |
fb1c8f93 IM |
191 | } |
192 | ||
193 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | |
194 | { | |
9a0b5817 | 195 | asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0" |
fb1c8f93 IM |
196 | : "=m" (rw->lock) : : "memory"); |
197 | } | |
198 | ||
1da177e4 | 199 | #endif /* __ASM_SPINLOCK_H */ |