Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef _I386_TLBFLUSH_H |
2 | #define _I386_TLBFLUSH_H | |
3 | ||
1da177e4 LT |
4 | #include <linux/mm.h> |
5 | #include <asm/processor.h> | |
6 | ||
7 | #define __flush_tlb() \ | |
8 | do { \ | |
9 | unsigned int tmpreg; \ | |
10 | \ | |
11 | __asm__ __volatile__( \ | |
12 | "movl %%cr3, %0; \n" \ | |
13 | "movl %0, %%cr3; # flush TLB \n" \ | |
14 | : "=r" (tmpreg) \ | |
15 | :: "memory"); \ | |
16 | } while (0) | |
17 | ||
18 | /* | |
19 | * Global pages have to be flushed a bit differently. Not a real | |
20 | * performance problem because this does not happen often. | |
21 | */ | |
22 | #define __flush_tlb_global() \ | |
23 | do { \ | |
ffaa8bd6 | 24 | unsigned int tmpreg, cr4, cr4_orig; \ |
1da177e4 LT |
25 | \ |
26 | __asm__ __volatile__( \ | |
ffaa8bd6 AA |
27 | "movl %%cr4, %2; # turn off PGE \n" \ |
28 | "movl %2, %1; \n" \ | |
29 | "andl %3, %1; \n" \ | |
30 | "movl %1, %%cr4; \n" \ | |
1da177e4 LT |
31 | "movl %%cr3, %0; \n" \ |
32 | "movl %0, %%cr3; # flush TLB \n" \ | |
33 | "movl %2, %%cr4; # turn PGE back on \n" \ | |
ffaa8bd6 AA |
34 | : "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \ |
35 | : "i" (~X86_CR4_PGE) \ | |
1da177e4 LT |
36 | : "memory"); \ |
37 | } while (0) | |
38 | ||
1da177e4 LT |
39 | # define __flush_tlb_all() \ |
40 | do { \ | |
41 | if (cpu_has_pge) \ | |
42 | __flush_tlb_global(); \ | |
43 | else \ | |
44 | __flush_tlb(); \ | |
45 | } while (0) | |
46 | ||
47 | #define cpu_has_invlpg (boot_cpu_data.x86 > 3) | |
48 | ||
49 | #define __flush_tlb_single(addr) \ | |
107878bb | 50 | __asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory") |
1da177e4 LT |
51 | |
52 | #ifdef CONFIG_X86_INVLPG | |
53 | # define __flush_tlb_one(addr) __flush_tlb_single(addr) | |
54 | #else | |
55 | # define __flush_tlb_one(addr) \ | |
56 | do { \ | |
57 | if (cpu_has_invlpg) \ | |
58 | __flush_tlb_single(addr); \ | |
59 | else \ | |
60 | __flush_tlb(); \ | |
61 | } while (0) | |
62 | #endif | |
63 | ||
64 | /* | |
65 | * TLB flushing: | |
66 | * | |
67 | * - flush_tlb() flushes the current mm struct TLBs | |
68 | * - flush_tlb_all() flushes all processes TLBs | |
69 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | |
70 | * - flush_tlb_page(vma, vmaddr) flushes one page | |
71 | * - flush_tlb_range(vma, start, end) flushes a range of pages | |
72 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | |
73 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables | |
74 | * | |
75 | * ..but the i386 has somewhat limited tlb flushing capabilities, | |
76 | * and page-granular flushes are available only on i486 and up. | |
77 | */ | |
78 | ||
79 | #ifndef CONFIG_SMP | |
80 | ||
81 | #define flush_tlb() __flush_tlb() | |
82 | #define flush_tlb_all() __flush_tlb_all() | |
83 | #define local_flush_tlb() __flush_tlb() | |
84 | ||
85 | static inline void flush_tlb_mm(struct mm_struct *mm) | |
86 | { | |
87 | if (mm == current->active_mm) | |
88 | __flush_tlb(); | |
89 | } | |
90 | ||
91 | static inline void flush_tlb_page(struct vm_area_struct *vma, | |
92 | unsigned long addr) | |
93 | { | |
94 | if (vma->vm_mm == current->active_mm) | |
95 | __flush_tlb_one(addr); | |
96 | } | |
97 | ||
98 | static inline void flush_tlb_range(struct vm_area_struct *vma, | |
99 | unsigned long start, unsigned long end) | |
100 | { | |
101 | if (vma->vm_mm == current->active_mm) | |
102 | __flush_tlb(); | |
103 | } | |
104 | ||
105 | #else | |
106 | ||
107 | #include <asm/smp.h> | |
108 | ||
109 | #define local_flush_tlb() \ | |
110 | __flush_tlb() | |
111 | ||
112 | extern void flush_tlb_all(void); | |
113 | extern void flush_tlb_current_task(void); | |
114 | extern void flush_tlb_mm(struct mm_struct *); | |
115 | extern void flush_tlb_page(struct vm_area_struct *, unsigned long); | |
116 | ||
117 | #define flush_tlb() flush_tlb_current_task() | |
118 | ||
119 | static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) | |
120 | { | |
121 | flush_tlb_mm(vma->vm_mm); | |
122 | } | |
123 | ||
124 | #define TLBSTATE_OK 1 | |
125 | #define TLBSTATE_LAZY 2 | |
126 | ||
127 | struct tlb_state | |
128 | { | |
129 | struct mm_struct *active_mm; | |
130 | int state; | |
131 | char __cacheline_padding[L1_CACHE_BYTES-8]; | |
132 | }; | |
133 | DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate); | |
134 | ||
135 | ||
136 | #endif | |
137 | ||
138 | #define flush_tlb_kernel_range(start, end) flush_tlb_all() | |
139 | ||
140 | static inline void flush_tlb_pgtables(struct mm_struct *mm, | |
141 | unsigned long start, unsigned long end) | |
142 | { | |
143 | /* i386 does not keep any page table caches in TLB */ | |
144 | } | |
145 | ||
146 | #endif /* _I386_TLBFLUSH_H */ |