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1da177e4 LT |
1 | /****************************************************************************/ |
2 | ||
3 | /* | |
4 | * mcfdebug.h -- ColdFire Debug Module support. | |
5 | * | |
6 | * (C) Copyright 2001, Lineo Inc. (www.lineo.com) | |
7 | */ | |
8 | ||
9 | /****************************************************************************/ | |
10 | #ifndef mcfdebug_h | |
11 | #define mcfdebug_h | |
12 | /****************************************************************************/ | |
13 | #include <linux/config.h> | |
14 | ||
15 | /* Define the debug module registers */ | |
16 | #define MCFDEBUG_CSR 0x0 /* Configuration status */ | |
17 | #define MCFDEBUG_BAAR 0x5 /* BDM address attribute */ | |
18 | #define MCFDEBUG_AATR 0x6 /* Address attribute trigger */ | |
19 | #define MCFDEBUG_TDR 0x7 /* Trigger definition */ | |
20 | #define MCFDEBUG_PBR 0x8 /* PC breakpoint */ | |
21 | #define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */ | |
22 | #define MCFDEBUG_ABHR 0xc /* High address breakpoint */ | |
23 | #define MCFDEBUG_ABLR 0xd /* Low address breakpoint */ | |
24 | #define MCFDEBUG_DBR 0xe /* Data breakpoint */ | |
25 | #define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */ | |
26 | ||
27 | /* Define some handy constants for the trigger definition register */ | |
28 | #define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */ | |
29 | #define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */ | |
30 | #define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */ | |
31 | #define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */ | |
32 | #define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */ | |
33 | #define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */ | |
34 | #define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */ | |
35 | #define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */ | |
36 | #define MCFDEBUG_TDR_EDLW2 0x10000000 | |
37 | #define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */ | |
38 | #define MCFDEBUG_TDR_EDWL2 0x08000000 | |
39 | #define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */ | |
40 | #define MCFDEBUG_TDR_EDWU2 0x04000000 | |
41 | #define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */ | |
42 | #define MCFDEBUG_TDR_EDLL2 0x02000000 | |
43 | #define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */ | |
44 | #define MCFDEBUG_TDR_EDLM2 0x01000000 | |
45 | #define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */ | |
46 | #define MCFDEBUG_TDR_EDUM2 0x00800000 | |
47 | #define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */ | |
48 | #define MCFDEBUG_TDR_EDUU2 0x00400000 | |
49 | #define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */ | |
50 | #define MCFDEBUG_TDR_DI2 0x00200000 | |
51 | #define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */ | |
52 | #define MCFDEBUG_TDR_EAI2 0x00100000 | |
53 | #define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */ | |
54 | #define MCFDEBUG_TDR_EAR2 0x00080000 | |
55 | #define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */ | |
56 | #define MCFDEBUG_TDR_EAL2 0x00040000 | |
57 | #define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */ | |
58 | #define MCFDEBUG_TDR_EPC2 0x00020000 | |
59 | #define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */ | |
60 | #define MCFDEBUG_TDR_PCI2 0x00010000 | |
61 | ||
62 | /* Constants for the address attribute trigger register */ | |
63 | #define MCFDEBUG_AAR_RESET 0x00000005 | |
64 | /* Fields not yet implemented */ | |
65 | ||
66 | /* And some definitions for the writable sections of the CSR */ | |
67 | #define MCFDEBUG_CSR_RESET 0x00100000 | |
68 | #define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */ | |
69 | #define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */ | |
70 | #define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */ | |
71 | #define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */ | |
72 | #define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */ | |
73 | #define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */ | |
74 | #define MCFDEBUG_CSR_DDC_WRITE 0x00001000 | |
75 | #define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */ | |
76 | #define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */ | |
77 | #define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */ | |
78 | #define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */ | |
79 | #define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */ | |
80 | #define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */ | |
81 | #define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */ | |
82 | ||
83 | /* Constants for the BDM address attribute register */ | |
84 | #define MCFDEBUG_BAAR_RESET 0x00000005 | |
85 | /* Fields not yet implemented */ | |
86 | ||
87 | ||
88 | /* This routine wrappers up the wdebug asm instruction so that the register | |
89 | * and value can be relatively easily specified. The biggest hassle here is | |
90 | * that the debug module instructions (2 longs) must be long word aligned and | |
91 | * some pointer fiddling is performed to ensure this. | |
92 | */ | |
93 | extern inline void wdebug(int reg, unsigned long data) { | |
94 | unsigned short dbg_spc[6]; | |
95 | unsigned short *dbg; | |
96 | ||
97 | // Force alignment to long word boundary | |
98 | dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc); | |
99 | ||
100 | // Build up the debug instruction | |
101 | dbg[0] = 0x2c80 | (reg & 0xf); | |
102 | dbg[1] = (data >> 16) & 0xffff; | |
103 | dbg[2] = data & 0xffff; | |
104 | dbg[3] = 0; | |
105 | ||
106 | // Perform the wdebug instruction | |
107 | #if 0 | |
108 | // This strain is for gas which doesn't have the wdebug instructions defined | |
109 | asm( "move.l %0, %%a0\n\t" | |
110 | ".word 0xfbd0\n\t" | |
111 | ".word 0x0003\n\t" | |
112 | :: "g" (dbg) : "a0"); | |
113 | #else | |
114 | // And this is for when it does | |
115 | asm( "wdebug (%0)" :: "a" (dbg)); | |
116 | #endif | |
117 | } | |
118 | ||
119 | #endif |