[deliverable/linux.git] / include / asm-m68knommu / system.h

#ifndef _M68KNOMMU_SYSTEM_H
#define _M68KNOMMU_SYSTEM_H

#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/entry.h>

/*
 * switch_to(n) should switch tasks to task ptr, first checking that
 * ptr isn't the current task, in which case it does nothing.  This
 * also clears the TS-flag if the task we switched to has used the
 * math co-processor latest.
 */
/*
 * switch_to() saves the extra registers, that are not saved
 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
 * a0-a1. Some of these are used by schedule() and its predecessors
 * and so we might get see unexpected behaviors when a task returns
 * with unexpected register values.
 *
 * syscall stores these registers itself and none of them are used
 * by syscall after the function in the syscall has been called.
 *
 * Beware that resume now expects *next to be in d1 and the offset of
 * tss to be in a1. This saves a few instructions as we no longer have
 * to push them onto the stack and read them back right after.
 *
 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
 *
 * Changed 96/09/19 by Andreas Schwab
 * pass prev in a0, next in a1, offset of tss in d1, and whether
 * the mm structures are shared in d2 (to avoid atc flushing).
 */
asmlinkage void resume(void);
#define switch_to(prev,next,last)				\
{								\
  void *_last;							\
  __asm__ __volatile__(						\
  	"movel	%1, %%a0\n\t"					\
	"movel	%2, %%a1\n\t"					\
	"jbsr resume\n\t"					\
	"movel	%%d1, %0\n\t"					\
       : "=d" (_last)						\
       : "d" (prev), "d" (next)					\
       : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1");	\
  (last) = _last;						\
}

#ifdef CONFIG_COLDFIRE
#define local_irq_enable() __asm__ __volatile__ (		\
	"move %/sr,%%d0\n\t"					\
	"andi.l #0xf8ff,%%d0\n\t"				\
	"move %%d0,%/sr\n"					\
	: /* no outputs */					\
	:							\
        : "cc", "%d0", "memory")
#define local_irq_disable() __asm__ __volatile__ (		\
	"move %/sr,%%d0\n\t"					\
	"ori.l #0x0700,%%d0\n\t"				\
	"move %%d0,%/sr\n"					\
	: /* no outputs */					\
	:							\
	: "cc", "%d0", "memory")
/* For spinlocks etc */
#define local_irq_save(x) __asm__ __volatile__ (		\
	"movew %%sr,%0\n\t"					\
	"movew #0x0700,%%d0\n\t"				\
	"or.l  %0,%%d0\n\t"					\
	"movew %%d0,%/sr"					\
	: "=d" (x)						\
	:							\
	: "cc", "%d0", "memory")
#else

/* portable version */ /* FIXME - see entry.h*/
#define ALLOWINT 0xf8ff

#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
#define local_irq_disable() asm volatile ("oriw  #0x0700,%%sr": : : "memory")
#endif

#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")

/* For spinlocks etc */
#ifndef local_irq_save
#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
#endif

#define	irqs_disabled()			\
({					\
	unsigned long flags;		\
	local_save_flags(flags);	\
	((flags & 0x0700) == 0x0700);	\
})

#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")

/*
 * Force strict CPU ordering.
 * Not really required on m68k...
 */
#define nop()  asm volatile ("nop"::)
#define mb()   asm volatile (""   : : :"memory")
#define rmb()  asm volatile (""   : : :"memory")
#define wmb()  asm volatile (""   : : :"memory")
#define set_rmb(var, value)    do { xchg(&var, value); } while (0)
#define set_mb(var, value)     set_rmb(var, value)

#ifdef CONFIG_SMP
#define smp_mb()	mb()
#define smp_rmb()	rmb()
#define smp_wmb()	wmb()
#define smp_read_barrier_depends()	read_barrier_depends()
#else
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#define smp_read_barrier_depends()	do { } while(0)
#endif

#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))

struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((volatile struct __xchg_dummy *)(x))

#ifndef CONFIG_RMW_INSNS
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
  unsigned long tmp, flags;

  local_irq_save(flags);

  switch (size) {
  case 1:
    __asm__ __volatile__
    ("moveb %2,%0\n\t"
     "moveb %1,%2"
    : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
    break;
  case 2:
    __asm__ __volatile__
    ("movew %2,%0\n\t"
     "movew %1,%2"
    : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
    break;
  case 4:
    __asm__ __volatile__
    ("movel %2,%0\n\t"
     "movel %1,%2"
    : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
    break;
  }
  local_irq_restore(flags);
  return tmp;
}
#else
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
	switch (size) {
	    case 1:
		__asm__ __volatile__
			("moveb %2,%0\n\t"
			 "1:\n\t"
			 "casb %0,%1,%2\n\t"
			 "jne 1b"
			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
		break;
	    case 2:
		__asm__ __volatile__
			("movew %2,%0\n\t"
			 "1:\n\t"
			 "casw %0,%1,%2\n\t"
			 "jne 1b"
			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
		break;
	    case 4:
		__asm__ __volatile__
			("movel %2,%0\n\t"
			 "1:\n\t"
			 "casl %0,%1,%2\n\t"
			 "jne 1b"
			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
		break;
	}
	return x;
}
#endif

/*
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 * store NEW in MEM.  Return the initial value in MEM.  Success is
 * indicated by comparing RETURN with OLD.
 */
#define __HAVE_ARCH_CMPXCHG	1

static __inline__ unsigned long
cmpxchg(volatile int *p, int old, int new)
{
	unsigned long flags;
	int prev;

	local_irq_save(flags);
	if ((prev = *p) == old)
		*p = new;
	local_irq_restore(flags);
	return(prev);
}


#ifdef CONFIG_M68332
#define HARD_RESET_NOW() ({		\
        local_irq_disable();		\
        asm("				\
	movew   #0x0000, 0xfffa6a;	\
        reset;				\
        /*movew #0x1557, 0xfffa44;*/	\
        /*movew #0x0155, 0xfffa46;*/	\
        moveal #0, %a0;			\
        movec %a0, %vbr;		\
        moveal 0, %sp;			\
        moveal 4, %a0;			\
        jmp (%a0);			\
        ");				\
})
#endif

#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \
	defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 )
#define HARD_RESET_NOW() ({		\
        local_irq_disable();		\
        asm("				\
        moveal #0x10c00000, %a0;	\
        moveb #0, 0xFFFFF300;		\
        moveal 0(%a0), %sp;		\
        moveal 4(%a0), %a0;		\
        jmp (%a0);			\
        ");				\
})
#endif

#ifdef CONFIG_COLDFIRE
#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
/*
 * Need to account for broken early mask of 5272 silicon. So don't
 * jump through the original start address. Jump strait into the
 * known start of the FLASH code.
 */
#define HARD_RESET_NOW() ({		\
        asm("				\
	movew #0x2700, %sr;		\
        jmp 0xf0000400;			\
        ");				\
})
#elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
      defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) || \
      defined(CONFIG_CLEOPATRA)
#define HARD_RESET_NOW() ({		\
        asm("				\
	movew #0x2700, %sr;		\
	moveal #0x10000044, %a0;	\
	movel #0xffffffff, (%a0);	\
	moveal #0x10000001, %a0;	\
	moveb #0x00, (%a0);		\
        moveal #0xf0000004, %a0;	\
        moveal (%a0), %a0;		\
        jmp (%a0);			\
        ");				\
})
#elif defined(CONFIG_M5272)
/*
 * Retrieve the boot address in flash using CSBR0 and CSOR0
 * find the reset vector at flash_address + 4 (e.g. 0x400)
 * remap it in the flash's current location (e.g. 0xf0000400)
 * and jump there.
 */ 
#define HARD_RESET_NOW() ({		\
	asm("				\
	movew #0x2700, %%sr;		\
	move.l	%0+0x40,%%d0;		\
	and.l	%0+0x44,%%d0;		\
	andi.l	#0xfffff000,%%d0;	\
	mov.l	%%d0,%%a0;		\
	or.l	4(%%a0),%%d0;		\
	mov.l	%%d0,%%a0;		\
	jmp (%%a0);"			\
	: /* No output */		\
	: "o" (*(char *)MCF_MBAR) );	\
})
#elif defined(CONFIG_M528x)
/*
 * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
 * that when set, resets the MCF528x.
 */
#define HARD_RESET_NOW() \
({						\
	unsigned char volatile *reset;		\
	asm("move.w	#0x2700, %sr");		\
	reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000));	\
	while(1)				\
	*reset |= (0x01 << 7);\
})
#elif defined(CONFIG_M523x)
#define HARD_RESET_NOW() ({		\
	asm("				\
	movew #0x2700, %sr;		\
	movel #0x01000000, %sp;		\
	moveal #0x40110000, %a0;	\
	moveb #0x80, (%a0);		\
	");				\
})
#elif defined(CONFIG_M520x)
	/*
	 * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register 
	 * RCR), that when set, resets the MCF5208.
	 */
#define HARD_RESET_NOW() 		\
({					\
	unsigned char volatile *reset;	\
	asm("move.w     #0x2700, %sr");	\
	reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000));	\
	while(1)			\
		*reset |= 0x80;		\
})
#else
#define HARD_RESET_NOW() ({		\
        asm("				\
	movew #0x2700, %sr;		\
        moveal #0x4, %a0;		\
        moveal (%a0), %a0;		\
        jmp (%a0);			\
        ");				\
})
#endif
#endif
#define arch_align_stack(x) (x)

#endif /* _M68KNOMMU_SYSTEM_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _M68KNOMMU_SYSTEM_H
	2	#define _M68KNOMMU_SYSTEM_H
	3
1da177e4 LT	4	#include <linux/linkage.h>
	5	#include <asm/segment.h>
	6	#include <asm/entry.h>
	7
	8	/*
	9	* switch_to(n) should switch tasks to task ptr, first checking that
	10	* ptr isn't the current task, in which case it does nothing. This
	11	* also clears the TS-flag if the task we switched to has used the
	12	* math co-processor latest.
	13	*/
	14	/*
	15	* switch_to() saves the extra registers, that are not saved
	16	* automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
	17	* a0-a1. Some of these are used by schedule() and its predecessors
	18	* and so we might get see unexpected behaviors when a task returns
	19	* with unexpected register values.
	20	*
	21	* syscall stores these registers itself and none of them are used
	22	* by syscall after the function in the syscall has been called.
	23	*
	24	* Beware that resume now expects *next to be in d1 and the offset of
	25	* tss to be in a1. This saves a few instructions as we no longer have
	26	* to push them onto the stack and read them back right after.
	27	*
	28	* 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
	29	*
	30	* Changed 96/09/19 by Andreas Schwab
	31	* pass prev in a0, next in a1, offset of tss in d1, and whether
	32	* the mm structures are shared in d2 (to avoid atc flushing).
	33	*/
	34	asmlinkage void resume(void);
	35	#define switch_to(prev,next,last) \
	36	{ \
	37	void *_last; \
	38	__asm__ __volatile__( \
	39	"movel %1, %%a0\n\t" \
	40	"movel %2, %%a1\n\t" \
	41	"jbsr resume\n\t" \
	42	"movel %%d1, %0\n\t" \
	43	: "=d" (_last) \
	44	: "d" (prev), "d" (next) \
	45	: "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
	46	(last) = _last; \
	47	}
	48
	49	#ifdef CONFIG_COLDFIRE
	50	#define local_irq_enable() __asm__ __volatile__ ( \
	51	"move %/sr,%%d0\n\t" \
	52	"andi.l #0xf8ff,%%d0\n\t" \
	53	"move %%d0,%/sr\n" \
	54	: /* no outputs */ \
	55	: \
	56	: "cc", "%d0", "memory")
	57	#define local_irq_disable() __asm__ __volatile__ ( \
	58	"move %/sr,%%d0\n\t" \
9c2aba48	59	"ori.l #0x0700,%%d0\n\t" \
1da177e4	60	"move %%d0,%/sr\n" \
9c2aba48 GU	61	: /* no outputs */ \
	62	: \
	63	: "cc", "%d0", "memory")
	64	/* For spinlocks etc */
	65	#define local_irq_save(x) __asm__ __volatile__ ( \
	66	"movew %%sr,%0\n\t" \
	67	"movew #0x0700,%%d0\n\t" \
	68	"or.l %0,%%d0\n\t" \
	69	"movew %%d0,%/sr" \
	70	: "=d" (x) \
1da177e4 LT	71	: \
	72	: "cc", "%d0", "memory")
	73	#else
	74
	75	/* portable version / / FIXME - see entry.h*/
	76	#define ALLOWINT 0xf8ff
	77
	78	#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
	79	#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
	80	#endif
	81
	82	#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
	83	#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
	84
	85	/* For spinlocks etc */
9c2aba48	86	#ifndef local_irq_save
1da177e4	87	#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
9c2aba48	88	#endif
1da177e4 LT	89
	90	#define irqs_disabled() \
	91	({ \
	92	unsigned long flags; \
	93	local_save_flags(flags); \
	94	((flags & 0x0700) == 0x0700); \
	95	})
	96
	97	#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
	98
	99	/*
	100	* Force strict CPU ordering.
	101	* Not really required on m68k...
	102	*/
	103	#define nop() asm volatile ("nop"::)
	104	#define mb() asm volatile ("" : : :"memory")
	105	#define rmb() asm volatile ("" : : :"memory")
	106	#define wmb() asm volatile ("" : : :"memory")
	107	#define set_rmb(var, value) do { xchg(&var, value); } while (0)
	108	#define set_mb(var, value) set_rmb(var, value)
1da177e4 LT	109
	110	#ifdef CONFIG_SMP
	111	#define smp_mb() mb()
	112	#define smp_rmb() rmb()
	113	#define smp_wmb() wmb()
	114	#define smp_read_barrier_depends() read_barrier_depends()
	115	#else
	116	#define smp_mb() barrier()
	117	#define smp_rmb() barrier()
	118	#define smp_wmb() barrier()
	119	#define smp_read_barrier_depends() do { } while(0)
	120	#endif
	121
	122	#define xchg(ptr,x) ((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
1da177e4 LT	123
	124	struct __xchg_dummy { unsigned long a[100]; };
	125	#define __xg(x) ((volatile struct __xchg_dummy *)(x))
	126
	127	#ifndef CONFIG_RMW_INSNS
	128	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
	129	{
	130	unsigned long tmp, flags;
	131
	132	local_irq_save(flags);
	133
	134	switch (size) {
	135	case 1:
	136	__asm__ __volatile__
	137	("moveb %2,%0\n\t"
	138	"moveb %1,%2"
	139	: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
	140	break;
	141	case 2:
	142	__asm__ __volatile__
	143	("movew %2,%0\n\t"
	144	"movew %1,%2"
	145	: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
	146	break;
	147	case 4:
	148	__asm__ __volatile__
	149	("movel %2,%0\n\t"
	150	"movel %1,%2"
	151	: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
	152	break;
	153	}
	154	local_irq_restore(flags);
	155	return tmp;
	156	}
	157	#else
	158	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
	159	{
	160	switch (size) {
	161	case 1:
	162	__asm__ __volatile__
	163	("moveb %2,%0\n\t"
	164	"1:\n\t"
	165	"casb %0,%1,%2\n\t"
	166	"jne 1b"
	167	: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
	168	break;
	169	case 2:
	170	__asm__ __volatile__
	171	("movew %2,%0\n\t"
	172	"1:\n\t"
	173	"casw %0,%1,%2\n\t"
	174	"jne 1b"
	175	: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
	176	break;
	177	case 4:
	178	__asm__ __volatile__
	179	("movel %2,%0\n\t"
	180	"1:\n\t"
	181	"casl %0,%1,%2\n\t"
	182	"jne 1b"
	183	: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
	184	break;
	185	}
	186	return x;
187	}
188	#endif
189
190	/*
191	* Atomic compare and exchange. Compare OLD with MEM, if identical,
192	* store NEW in MEM. Return the initial value in MEM. Success is
193	* indicated by comparing RETURN with OLD.
194	*/
195	#define __HAVE_ARCH_CMPXCHG 1
196
197	static __inline__ unsigned long
198	cmpxchg(volatile int *p, int old, int new)
199	{
200	unsigned long flags;
201	int prev;
202
203	local_irq_save(flags);
204	if ((prev = *p) == old)
205	*p = new;
206	local_irq_restore(flags);
207	return(prev);
208	}
209
210
211	#ifdef CONFIG_M68332
212	#define HARD_RESET_NOW() ({ \
213	local_irq_disable(); \
214	asm(" \
215	movew #0x0000, 0xfffa6a; \
216	reset; \
217	/movew #0x1557, 0xfffa44;/ \
218	/movew #0x0155, 0xfffa46;/ \
219	moveal #0, %a0; \
220	movec %a0, %vbr; \
221	moveal 0, %sp; \
222	moveal 4, %a0; \
223	jmp (%a0); \
224	"); \
225	})
226	#endif
227
228	#if defined( CONFIG_M68328 ) \|\| defined( CONFIG_M68EZ328 ) \|\| \
229	defined (CONFIG_M68360) \|\| defined( CONFIG_M68VZ328 )
230	#define HARD_RESET_NOW() ({ \
231	local_irq_disable(); \
232	asm(" \
233	moveal #0x10c00000, %a0; \
234	moveb #0, 0xFFFFF300; \
235	moveal 0(%a0), %sp; \
236	moveal 4(%a0), %a0; \
237	jmp (%a0); \
238	"); \
239	})
240	#endif
241
242	#ifdef CONFIG_COLDFIRE
243	#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
244	/*
9c2aba48 GU	245	* Need to account for broken early mask of 5272 silicon. So don't
	246	* jump through the original start address. Jump strait into the
	247	* known start of the FLASH code.
1da177e4 LT	248	*/
	249	#define HARD_RESET_NOW() ({ \
	250	asm(" \
	251	movew #0x2700, %sr; \
	252	jmp 0xf0000400; \
	253	"); \
	254	})
9c2aba48 GU	255	#elif defined(CONFIG_NETtel) \|\| defined(CONFIG_eLIA) \|\| \
	256	defined(CONFIG_DISKtel) \|\| defined(CONFIG_SECUREEDGEMP3) \|\| \
	257	defined(CONFIG_CLEOPATRA)
1da177e4 LT	258	#define HARD_RESET_NOW() ({ \
	259	asm(" \
	260	movew #0x2700, %sr; \
	261	moveal #0x10000044, %a0; \
	262	movel #0xffffffff, (%a0); \
	263	moveal #0x10000001, %a0; \
	264	moveb #0x00, (%a0); \
	265	moveal #0xf0000004, %a0; \
	266	moveal (%a0), %a0; \
	267	jmp (%a0); \
	268	"); \
	269	})
9c2aba48 GU	270	#elif defined(CONFIG_M5272)
	271	/*
	272	* Retrieve the boot address in flash using CSBR0 and CSOR0
	273	* find the reset vector at flash_address + 4 (e.g. 0x400)
	274	* remap it in the flash's current location (e.g. 0xf0000400)
	275	* and jump there.
	276	*/
	277	#define HARD_RESET_NOW() ({ \
	278	asm(" \
	279	movew #0x2700, %%sr; \
	280	move.l %0+0x40,%%d0; \
	281	and.l %0+0x44,%%d0; \
	282	andi.l #0xfffff000,%%d0; \
	283	mov.l %%d0,%%a0; \
	284	or.l 4(%%a0),%%d0; \
	285	mov.l %%d0,%%a0; \
	286	jmp (%%a0);" \
	287	: /* No output */ \
	288	: "o" ((char )MCF_MBAR) ); \
	289	})
1da177e4 LT	290	#elif defined(CONFIG_M528x)
	291	/*
	292	* The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
	293	* that when set, resets the MCF528x.
	294	*/
	295	#define HARD_RESET_NOW() \
	296	({ \
	297	unsigned char volatile *reset; \
	298	asm("move.w #0x2700, %sr"); \
020f9e16	299	reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \
1da177e4 LT	300	while(1) \
	301	*reset \|= (0x01 << 7);\
	302	})
9c2aba48 GU	303	#elif defined(CONFIG_M523x)
	304	#define HARD_RESET_NOW() ({ \
	305	asm(" \
	306	movew #0x2700, %sr; \
	307	movel #0x01000000, %sp; \
	308	moveal #0x40110000, %a0; \
	309	moveb #0x80, (%a0); \
	310	"); \
	311	})
01824853 GU	312	#elif defined(CONFIG_M520x)
	313	/*
	314	* The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register
	315	* RCR), that when set, resets the MCF5208.
	316	*/
	317	#define HARD_RESET_NOW() \
	318	({ \
	319	unsigned char volatile *reset; \
	320	asm("move.w #0x2700, %sr"); \
020f9e16	321	reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \
01824853 GU	322	while(1) \
	323	*reset \|= 0x80; \
	324	})
1da177e4 LT	325	#else
	326	#define HARD_RESET_NOW() ({ \
	327	asm(" \
	328	movew #0x2700, %sr; \
	329	moveal #0x4, %a0; \
	330	moveal (%a0), %a0; \
	331	jmp (%a0); \
	332	"); \
	333	})
	334	#endif
	335	#endif
	336	#define arch_align_stack(x) (x)
	337
	338	#endif /* _M68KNOMMU_SYSTEM_H */