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1da177e4 LT |
1 | /* |
2 | * cpu.h: Values of the PRId register used to match up | |
3 | * various MIPS cpu types. | |
4 | * | |
5 | * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) | |
4194318c | 6 | * Copyright (C) 2004 Maciej W. Rozycki |
1da177e4 LT |
7 | */ |
8 | #ifndef _ASM_CPU_H | |
9 | #define _ASM_CPU_H | |
10 | ||
11 | /* Assigned Company values for bits 23:16 of the PRId Register | |
12 | (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from | |
13 | MTI, the PRId register is defined in this (backwards compatible) | |
14 | way: | |
15 | ||
16 | +----------------+----------------+----------------+----------------+ | |
17 | | Company Options| Company ID | Processor ID | Revision | | |
18 | +----------------+----------------+----------------+----------------+ | |
19 | 31 24 23 16 15 8 7 | |
20 | ||
21 | I don't have docs for all the previous processors, but my impression is | |
22 | that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 | |
23 | spec. | |
24 | */ | |
25 | ||
55a6feb6 RB |
26 | #define PRID_COMP_LEGACY 0x000000 |
27 | #define PRID_COMP_MIPS 0x010000 | |
28 | #define PRID_COMP_BROADCOM 0x020000 | |
29 | #define PRID_COMP_ALCHEMY 0x030000 | |
30 | #define PRID_COMP_SIBYTE 0x040000 | |
31 | #define PRID_COMP_SANDCRAFT 0x050000 | |
32 | #define PRID_COMP_PHILIPS 0x060000 | |
33 | #define PRID_COMP_TOSHIBA 0x070000 | |
34 | #define PRID_COMP_LSI 0x080000 | |
35 | #define PRID_COMP_LEXRA 0x0b0000 | |
36 | ||
1da177e4 LT |
37 | |
38 | /* | |
39 | * Assigned values for the product ID register. In order to detect a | |
40 | * certain CPU type exactly eventually additional registers may need to | |
41 | * be examined. These are valid when 23:16 == PRID_COMP_LEGACY | |
42 | */ | |
43 | #define PRID_IMP_R2000 0x0100 | |
44 | #define PRID_IMP_AU1_REV1 0x0100 | |
45 | #define PRID_IMP_AU1_REV2 0x0200 | |
46 | #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ | |
47 | #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ | |
48 | #define PRID_IMP_R4000 0x0400 | |
49 | #define PRID_IMP_R6000A 0x0600 | |
50 | #define PRID_IMP_R10000 0x0900 | |
51 | #define PRID_IMP_R4300 0x0b00 | |
52 | #define PRID_IMP_VR41XX 0x0c00 | |
53 | #define PRID_IMP_R12000 0x0e00 | |
54 | #define PRID_IMP_R8000 0x1000 | |
55 | #define PRID_IMP_R4600 0x2000 | |
56 | #define PRID_IMP_R4700 0x2100 | |
57 | #define PRID_IMP_TX39 0x2200 | |
58 | #define PRID_IMP_R4640 0x2200 | |
59 | #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ | |
60 | #define PRID_IMP_R5000 0x2300 | |
61 | #define PRID_IMP_TX49 0x2d00 | |
62 | #define PRID_IMP_SONIC 0x2400 | |
63 | #define PRID_IMP_MAGIC 0x2500 | |
64 | #define PRID_IMP_RM7000 0x2700 | |
65 | #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ | |
66 | #define PRID_IMP_RM9000 0x3400 | |
67 | #define PRID_IMP_R5432 0x5400 | |
68 | #define PRID_IMP_R5500 0x5500 | |
69 | #define PRID_IMP_4KC 0x8000 | |
70 | #define PRID_IMP_5KC 0x8100 | |
71 | #define PRID_IMP_20KC 0x8200 | |
72 | #define PRID_IMP_4KEC 0x8400 | |
73 | #define PRID_IMP_4KSC 0x8600 | |
74 | #define PRID_IMP_25KF 0x8800 | |
75 | #define PRID_IMP_5KE 0x8900 | |
76 | #define PRID_IMP_4KECR2 0x9000 | |
77 | #define PRID_IMP_4KEMPR2 0x9100 | |
78 | #define PRID_IMP_4KSD 0x9200 | |
79 | #define PRID_IMP_24K 0x9300 | |
e50c0a8f | 80 | #define PRID_IMP_24KE 0x9600 |
1da177e4 LT |
81 | |
82 | #define PRID_IMP_UNKNOWN 0xff00 | |
83 | ||
84 | /* | |
85 | * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE | |
86 | */ | |
87 | ||
88 | #define PRID_IMP_SB1 0x0100 | |
89 | ||
90 | /* | |
91 | * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT | |
92 | */ | |
93 | ||
94 | #define PRID_IMP_SR71000 0x0400 | |
95 | ||
96 | /* | |
97 | * Definitions for 7:0 on legacy processors | |
98 | */ | |
99 | ||
100 | ||
101 | #define PRID_REV_TX4927 0x0022 | |
102 | #define PRID_REV_TX4937 0x0030 | |
103 | #define PRID_REV_R4400 0x0040 | |
104 | #define PRID_REV_R3000A 0x0030 | |
105 | #define PRID_REV_R3000 0x0020 | |
106 | #define PRID_REV_R2000A 0x0010 | |
107 | #define PRID_REV_TX3912 0x0010 | |
108 | #define PRID_REV_TX3922 0x0030 | |
109 | #define PRID_REV_TX3927 0x0040 | |
110 | #define PRID_REV_VR4111 0x0050 | |
111 | #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ | |
112 | #define PRID_REV_VR4121 0x0060 | |
113 | #define PRID_REV_VR4122 0x0070 | |
114 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ | |
115 | #define PRID_REV_VR4130 0x0080 | |
116 | ||
117 | /* | |
118 | * FPU implementation/revision register (CP1 control register 0). | |
119 | * | |
120 | * +---------------------------------+----------------+----------------+ | |
121 | * | 0 | Implementation | Revision | | |
122 | * +---------------------------------+----------------+----------------+ | |
123 | * 31 16 15 8 7 0 | |
124 | */ | |
125 | ||
126 | #define FPIR_IMP_NONE 0x0000 | |
127 | ||
128 | #define CPU_UNKNOWN 0 | |
129 | #define CPU_R2000 1 | |
130 | #define CPU_R3000 2 | |
131 | #define CPU_R3000A 3 | |
132 | #define CPU_R3041 4 | |
133 | #define CPU_R3051 5 | |
134 | #define CPU_R3052 6 | |
135 | #define CPU_R3081 7 | |
136 | #define CPU_R3081E 8 | |
137 | #define CPU_R4000PC 9 | |
138 | #define CPU_R4000SC 10 | |
139 | #define CPU_R4000MC 11 | |
140 | #define CPU_R4200 12 | |
141 | #define CPU_R4400PC 13 | |
142 | #define CPU_R4400SC 14 | |
143 | #define CPU_R4400MC 15 | |
144 | #define CPU_R4600 16 | |
145 | #define CPU_R6000 17 | |
146 | #define CPU_R6000A 18 | |
147 | #define CPU_R8000 19 | |
148 | #define CPU_R10000 20 | |
149 | #define CPU_R12000 21 | |
150 | #define CPU_R4300 22 | |
151 | #define CPU_R4650 23 | |
152 | #define CPU_R4700 24 | |
153 | #define CPU_R5000 25 | |
154 | #define CPU_R5000A 26 | |
155 | #define CPU_R4640 27 | |
156 | #define CPU_NEVADA 28 | |
157 | #define CPU_RM7000 29 | |
158 | #define CPU_R5432 30 | |
159 | #define CPU_4KC 31 | |
160 | #define CPU_5KC 32 | |
161 | #define CPU_R4310 33 | |
162 | #define CPU_SB1 34 | |
163 | #define CPU_TX3912 35 | |
164 | #define CPU_TX3922 36 | |
165 | #define CPU_TX3927 37 | |
166 | #define CPU_AU1000 38 | |
167 | #define CPU_4KEC 39 | |
168 | #define CPU_4KSC 40 | |
169 | #define CPU_VR41XX 41 | |
170 | #define CPU_R5500 42 | |
171 | #define CPU_TX49XX 43 | |
172 | #define CPU_AU1500 44 | |
173 | #define CPU_20KC 45 | |
174 | #define CPU_VR4111 46 | |
175 | #define CPU_VR4121 47 | |
176 | #define CPU_VR4122 48 | |
177 | #define CPU_VR4131 49 | |
178 | #define CPU_VR4181 50 | |
179 | #define CPU_VR4181A 51 | |
180 | #define CPU_AU1100 52 | |
181 | #define CPU_SR71000 53 | |
182 | #define CPU_RM9000 54 | |
183 | #define CPU_25KF 55 | |
184 | #define CPU_VR4133 56 | |
185 | #define CPU_AU1550 57 | |
186 | #define CPU_24K 58 | |
e3ad1c23 PP |
187 | #define CPU_AU1200 59 |
188 | #define CPU_LAST 59 | |
1da177e4 LT |
189 | |
190 | /* | |
191 | * ISA Level encodings | |
192 | * | |
193 | */ | |
194 | #define MIPS_CPU_ISA_I 0x00000001 | |
195 | #define MIPS_CPU_ISA_II 0x00000002 | |
196 | #define MIPS_CPU_ISA_III 0x00008003 | |
197 | #define MIPS_CPU_ISA_IV 0x00008004 | |
198 | #define MIPS_CPU_ISA_V 0x00008005 | |
199 | #define MIPS_CPU_ISA_M32 0x00000020 | |
200 | #define MIPS_CPU_ISA_M64 0x00008040 | |
201 | ||
202 | /* | |
203 | * Bit 15 encodes if an ISA level supports 64-bit operations. | |
204 | */ | |
205 | #define MIPS_CPU_ISA_64BIT 0x00008000 | |
206 | ||
207 | /* | |
208 | * CPU Option encodings | |
209 | */ | |
210 | #define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ | |
211 | /* Leave a spare bit for variant MMU types... */ | |
212 | #define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */ | |
213 | #define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */ | |
214 | #define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */ | |
215 | #define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */ | |
216 | #define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */ | |
217 | #define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */ | |
1da177e4 LT |
218 | #define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ |
219 | #define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ | |
220 | #define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ | |
221 | #define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ | |
222 | #define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ | |
223 | #define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ | |
224 | #define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ | |
225 | #define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ | |
226 | #define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */ | |
227 | #define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ | |
228 | ||
4194318c RB |
229 | /* |
230 | * CPU ASE encodings | |
231 | */ | |
232 | #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ | |
233 | #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ | |
234 | #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ | |
235 | #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ | |
e50c0a8f | 236 | #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ |
4194318c | 237 | |
1da177e4 | 238 | #endif /* _ASM_CPU_H */ |