[deliverable/linux.git] / include / asm-mips / futex.h

#ifndef _ASM_FUTEX_H
#define _ASM_FUTEX_H

#ifdef __KERNEL__

#include <linux/futex.h>
#include <asm/errno.h>
#include <asm/uaccess.h>
#include <asm/war.h>

#ifdef CONFIG_SMP
#define __FUTEX_SMP_SYNC "	sync					\n"
#else
#define __FUTEX_SMP_SYNC
#endif

#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)		\
{									\
	if (cpu_has_llsc && R10000_LLSC_WAR) {				\
		__asm__ __volatile__(					\
		"	.set	push				\n"	\
		"	.set	noat				\n"	\
		"	.set	mips3				\n"	\
		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
		"	.set	mips0				\n"	\
		"	" insn	"				\n"	\
		"	.set	mips3				\n"	\
		"2:	sc	$1, %2				\n"	\
		"	beqzl	$1, 1b				\n"	\
		__FUTEX_SMP_SYNC					\
		"3:						\n"	\
		"	.set	pop				\n"	\
		"	.set	mips0				\n"	\
		"	.section .fixup,\"ax\"			\n"	\
		"4:	li	%0, %6				\n"	\
		"	j	2b				\n"	\
		"	.previous				\n"	\
		"	.section __ex_table,\"a\"		\n"	\
		"	"__UA_ADDR "\t1b, 4b			\n"	\
		"	"__UA_ADDR "\t2b, 4b			\n"	\
		"	.previous				\n"	\
		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
		: "memory");						\
	} else if (cpu_has_llsc) {					\
		__asm__ __volatile__(					\
		"	.set	push				\n"	\
		"	.set	noat				\n"	\
		"	.set	mips3				\n"	\
		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
		"	.set	mips0				\n"	\
		"	" insn	"				\n"	\
		"	.set	mips3				\n"	\
		"2:	sc	$1, %2				\n"	\
		"	beqz	$1, 1b				\n"	\
		__FUTEX_SMP_SYNC					\
		"3:						\n"	\
		"	.set	pop				\n"	\
		"	.set	mips0				\n"	\
		"	.section .fixup,\"ax\"			\n"	\
		"4:	li	%0, %6				\n"	\
		"	j	2b				\n"	\
		"	.previous				\n"	\
		"	.section __ex_table,\"a\"		\n"	\
		"	"__UA_ADDR "\t1b, 4b			\n"	\
		"	"__UA_ADDR "\t2b, 4b			\n"	\
		"	.previous				\n"	\
		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
		: "memory");						\
	} else								\
		ret = -ENOSYS;						\
}

static inline int
futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
{
	int op = (encoded_op >> 28) & 7;
	int cmp = (encoded_op >> 24) & 15;
	int oparg = (encoded_op << 8) >> 20;
	int cmparg = (encoded_op << 20) >> 20;
	int oldval = 0, ret;
	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
		oparg = 1 << oparg;

	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
		return -EFAULT;

	inc_preempt_count();

	switch (op) {
	case FUTEX_OP_SET:
		__futex_atomic_op("move	$1, %z5", ret, oldval, uaddr, oparg);
		break;

	case FUTEX_OP_ADD:
		__futex_atomic_op("addu	$1, %1, %z5",
		                  ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_OR:
		__futex_atomic_op("or	$1, %1, %z5",
		                  ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ANDN:
		__futex_atomic_op("and	$1, %1, %z5",
		                  ret, oldval, uaddr, ~oparg);
		break;
	case FUTEX_OP_XOR:
		__futex_atomic_op("xor	$1, %1, %z5",
		                  ret, oldval, uaddr, oparg);
		break;
	default:
		ret = -ENOSYS;
	}

	dec_preempt_count();

	if (!ret) {
		switch (cmp) {
		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
		default: ret = -ENOSYS;
		}
	}
	return ret;
}

static inline int
futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
{
	int retval;

	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
		return -EFAULT;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		__asm__ __volatile__(
		"# futex_atomic_cmpxchg_inatomic			\n"
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	ll	%0, %2					\n"
		"	bne	%0, %z3, 3f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z4					\n"
		"	.set	mips3					\n"
		"2:	sc	$1, %1					\n"
		"	beqzl	$1, 1b					\n"
		__FUTEX_SMP_SYNC
		"3:							\n"
		"	.set	pop					\n"
		"	.section .fixup,\"ax\"				\n"
		"4:	li	%0, %5					\n"
		"	j	3b					\n"
		"	.previous					\n"
		"	.section __ex_table,\"a\"			\n"
		"	"__UA_ADDR "\t1b, 4b				\n"
		"	"__UA_ADDR "\t2b, 4b				\n"
		"	.previous					\n"
		: "=&r" (retval), "=R" (*uaddr)
		: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
		: "memory");
	} else if (cpu_has_llsc) {
		__asm__ __volatile__(
		"# futex_atomic_cmpxchg_inatomic			\n"
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	ll	%0, %2					\n"
		"	bne	%0, %z3, 3f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z4					\n"
		"	.set	mips3					\n"
		"2:	sc	$1, %1					\n"
		"	beqz	$1, 1b					\n"
		__FUTEX_SMP_SYNC
		"3:							\n"
		"	.set	pop					\n"
		"	.section .fixup,\"ax\"				\n"
		"4:	li	%0, %5					\n"
		"	j	3b					\n"
		"	.previous					\n"
		"	.section __ex_table,\"a\"			\n"
		"	"__UA_ADDR "\t1b, 4b				\n"
		"	"__UA_ADDR "\t2b, 4b				\n"
		"	.previous					\n"
		: "=&r" (retval), "=R" (*uaddr)
		: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
		: "memory");
	} else
		return -ENOSYS;

	return retval;
}

#endif
#endif
Commit	Line	Data
4732efbe JJ	1	#ifndef _ASM_FUTEX_H
	2	#define _ASM_FUTEX_H
	3
	4	#ifdef __KERNEL__
	5
	6	#include <linux/futex.h>
	7	#include <asm/errno.h>
	8	#include <asm/uaccess.h>
6ee1da94	9	#include <asm/war.h>
4732efbe	10
ebfaebae RB	11	#ifdef CONFIG_SMP
	12	#define __FUTEX_SMP_SYNC " sync \n"
	13	#else
	14	#define __FUTEX_SMP_SYNC
	15	#endif
	16
	17	#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
	18	{ \
6ee1da94 RB	19	if (cpu_has_llsc && R10000_LLSC_WAR) { \
	20	__asm__ __volatile__( \
	21	" .set push \n" \
	22	" .set noat \n" \
	23	" .set mips3 \n" \
0307e8d0	24	"1: ll %1, %4 # __futex_atomic_op \n" \
6ee1da94 RB	25	" .set mips0 \n" \
	26	" " insn " \n" \
	27	" .set mips3 \n" \
0307e8d0	28	"2: sc $1, %2 \n" \
6ee1da94 RB	29	" beqzl $1, 1b \n" \
	30	__FUTEX_SMP_SYNC \
	31	"3: \n" \
	32	" .set pop \n" \
	33	" .set mips0 \n" \
	34	" .section .fixup,\"ax\" \n" \
0307e8d0	35	"4: li %0, %6 \n" \
6ee1da94 RB	36	" j 2b \n" \
	37	" .previous \n" \
	38	" .section __ex_table,\"a\" \n" \
	39	" "__UA_ADDR "\t1b, 4b \n" \
	40	" "__UA_ADDR "\t2b, 4b \n" \
	41	" .previous \n" \
0307e8d0 AN	42	: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
	43	: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
	44	: "memory"); \
6ee1da94 RB	45	} else if (cpu_has_llsc) { \
	46	__asm__ __volatile__( \
	47	" .set push \n" \
	48	" .set noat \n" \
	49	" .set mips3 \n" \
0307e8d0	50	"1: ll %1, %4 # __futex_atomic_op \n" \
6ee1da94 RB	51	" .set mips0 \n" \
	52	" " insn " \n" \
	53	" .set mips3 \n" \
0307e8d0	54	"2: sc $1, %2 \n" \
6ee1da94 RB	55	" beqz $1, 1b \n" \
	56	__FUTEX_SMP_SYNC \
	57	"3: \n" \
	58	" .set pop \n" \
	59	" .set mips0 \n" \
	60	" .section .fixup,\"ax\" \n" \
0307e8d0	61	"4: li %0, %6 \n" \
6ee1da94 RB	62	" j 2b \n" \
	63	" .previous \n" \
	64	" .section __ex_table,\"a\" \n" \
	65	" "__UA_ADDR "\t1b, 4b \n" \
	66	" "__UA_ADDR "\t2b, 4b \n" \
	67	" .previous \n" \
0307e8d0 AN	68	: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
	69	: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
	70	: "memory"); \
6ee1da94 RB	71	} else \
6ee1da94 RB	72	ret = -ENOSYS; \
ebfaebae RB	73	}
ebfaebae RB	74
4732efbe JJ	75	static inline int
	76	futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
	77	{
	78	int op = (encoded_op >> 28) & 7;
	79	int cmp = (encoded_op >> 24) & 15;
	80	int oparg = (encoded_op << 8) >> 20;
	81	int cmparg = (encoded_op << 20) >> 20;
	82	int oldval = 0, ret;
	83	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
	84	oparg = 1 << oparg;
	85
	86	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
	87	return -EFAULT;
	88
	89	inc_preempt_count();
	90
	91	switch (op) {
	92	case FUTEX_OP_SET:
0307e8d0	93	__futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
ebfaebae RB	94	break;
ebfaebae RB	95
4732efbe	96	case FUTEX_OP_ADD:
0307e8d0	97	__futex_atomic_op("addu $1, %1, %z5",
ebfaebae RB	98	ret, oldval, uaddr, oparg);
ebfaebae RB	99	break;
4732efbe	100	case FUTEX_OP_OR:
0307e8d0	101	__futex_atomic_op("or $1, %1, %z5",
ebfaebae RB	102	ret, oldval, uaddr, oparg);
ebfaebae RB	103	break;
4732efbe	104	case FUTEX_OP_ANDN:
0307e8d0	105	__futex_atomic_op("and $1, %1, %z5",
ebfaebae RB	106	ret, oldval, uaddr, ~oparg);
ebfaebae RB	107	break;
4732efbe	108	case FUTEX_OP_XOR:
0307e8d0	109	__futex_atomic_op("xor $1, %1, %z5",
ebfaebae RB	110	ret, oldval, uaddr, oparg);
ebfaebae RB	111	break;
4732efbe JJ	112	default:
	113	ret = -ENOSYS;
	114	}
	115
	116	dec_preempt_count();
	117
	118	if (!ret) {
	119	switch (cmp) {
	120	case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
	121	case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
	122	case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
	123	case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
	124	case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
	125	case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
	126	default: ret = -ENOSYS;
	127	}
	128	}
	129	return ret;
	130	}
	131
e9056f13	132	static inline int
8f17d3a5	133	futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
e9056f13	134	{
6ee1da94 RB	135	int retval;
	136
	137	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
	138	return -EFAULT;
	139
	140	if (cpu_has_llsc && R10000_LLSC_WAR) {
	141	__asm__ __volatile__(
	142	"# futex_atomic_cmpxchg_inatomic \n"
	143	" .set push \n"
	144	" .set noat \n"
	145	" .set mips3 \n"
	146	"1: ll %0, %2 \n"
	147	" bne %0, %z3, 3f \n"
	148	" .set mips0 \n"
	149	" move $1, %z4 \n"
	150	" .set mips3 \n"
	151	"2: sc $1, %1 \n"
	152	" beqzl $1, 1b \n"
	153	__FUTEX_SMP_SYNC
	154	"3: \n"
	155	" .set pop \n"
	156	" .section .fixup,\"ax\" \n"
	157	"4: li %0, %5 \n"
	158	" j 3b \n"
	159	" .previous \n"
	160	" .section __ex_table,\"a\" \n"
	161	" "__UA_ADDR "\t1b, 4b \n"
	162	" "__UA_ADDR "\t2b, 4b \n"
	163	" .previous \n"
	164	: "=&r" (retval), "=R" (*uaddr)
	165	: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
	166	: "memory");
	167	} else if (cpu_has_llsc) {
	168	__asm__ __volatile__(
	169	"# futex_atomic_cmpxchg_inatomic \n"
	170	" .set push \n"
	171	" .set noat \n"
	172	" .set mips3 \n"
	173	"1: ll %0, %2 \n"
	174	" bne %0, %z3, 3f \n"
	175	" .set mips0 \n"
	176	" move $1, %z4 \n"
	177	" .set mips3 \n"
	178	"2: sc $1, %1 \n"
	179	" beqz $1, 1b \n"
	180	__FUTEX_SMP_SYNC
	181	"3: \n"
	182	" .set pop \n"
	183	" .section .fixup,\"ax\" \n"
	184	"4: li %0, %5 \n"
	185	" j 3b \n"
	186	" .previous \n"
	187	" .section __ex_table,\"a\" \n"
	188	" "__UA_ADDR "\t1b, 4b \n"
	189	" "__UA_ADDR "\t2b, 4b \n"
	190	" .previous \n"
	191	: "=&r" (retval), "=R" (*uaddr)
	192	: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
	193	: "memory");
	194	} else
	195	return -ENOSYS;
	196
	197	return retval;
e9056f13 IM	198	}
e9056f13 IM	199
4732efbe JJ	200	#endif
4732efbe JJ	201	#endif