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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle | |
7 | * Copyright (C) 1996 by Paul M. Antoine | |
8 | * Copyright (C) 1999 Silicon Graphics | |
9 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
10 | */ | |
192ef366 RB |
11 | #ifndef _ASM_IRQFLAGS_H |
12 | #define _ASM_IRQFLAGS_H | |
13 | ||
14 | #ifndef __ASSEMBLY__ | |
1da177e4 LT |
15 | |
16 | #include <asm/hazards.h> | |
17 | ||
18 | __asm__ ( | |
192ef366 | 19 | " .macro raw_local_irq_enable \n" |
ff88f8a3 RB |
20 | " .set push \n" |
21 | " .set reorder \n" | |
22 | " .set noat \n" | |
41c594ab RB |
23 | #ifdef CONFIG_MIPS_MT_SMTC |
24 | " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" | |
25 | " ori $1, 0x400 \n" | |
26 | " xori $1, 0x400 \n" | |
27 | " mtc0 $1, $2, 1 \n" | |
28 | #elif defined(CONFIG_CPU_MIPSR2) | |
ff88f8a3 RB |
29 | " ei \n" |
30 | #else | |
31 | " mfc0 $1,$12 \n" | |
32 | " ori $1,0x1f \n" | |
33 | " xori $1,0x1e \n" | |
34 | " mtc0 $1,$12 \n" | |
35 | #endif | |
36 | " irq_enable_hazard \n" | |
37 | " .set pop \n" | |
38 | " .endm"); | |
1da177e4 | 39 | |
192ef366 | 40 | static inline void raw_local_irq_enable(void) |
1da177e4 LT |
41 | { |
42 | __asm__ __volatile__( | |
192ef366 | 43 | "raw_local_irq_enable" |
1da177e4 LT |
44 | : /* no outputs */ |
45 | : /* no inputs */ | |
46 | : "memory"); | |
47 | } | |
48 | ||
49 | /* | |
50 | * For cli() we have to insert nops to make sure that the new value | |
51 | * has actually arrived in the status register before the end of this | |
52 | * macro. | |
53 | * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs | |
54 | * no nops at all. | |
55 | */ | |
c226f260 AN |
56 | /* |
57 | * For TX49, operating only IE bit is not enough. | |
58 | * | |
59 | * If mfc0 $12 follows store and the mfc0 is last instruction of a | |
60 | * page and fetching the next instruction causes TLB miss, the result | |
61 | * of the mfc0 might wrongly contain EXL bit. | |
62 | * | |
63 | * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 | |
64 | * | |
65 | * Workaround: mask EXL bit of the result or place a nop before mfc0. | |
66 | */ | |
1da177e4 | 67 | __asm__ ( |
192ef366 | 68 | " .macro raw_local_irq_disable\n" |
ff88f8a3 RB |
69 | " .set push \n" |
70 | " .set noat \n" | |
41c594ab RB |
71 | #ifdef CONFIG_MIPS_MT_SMTC |
72 | " mfc0 $1, $2, 1 \n" | |
73 | " ori $1, 0x400 \n" | |
74 | " .set noreorder \n" | |
75 | " mtc0 $1, $2, 1 \n" | |
76 | #elif defined(CONFIG_CPU_MIPSR2) | |
ff88f8a3 RB |
77 | " di \n" |
78 | #else | |
79 | " mfc0 $1,$12 \n" | |
c226f260 AN |
80 | " ori $1,0x1f \n" |
81 | " xori $1,0x1f \n" | |
ff88f8a3 RB |
82 | " .set noreorder \n" |
83 | " mtc0 $1,$12 \n" | |
84 | #endif | |
85 | " irq_disable_hazard \n" | |
86 | " .set pop \n" | |
87 | " .endm \n"); | |
1da177e4 | 88 | |
192ef366 | 89 | static inline void raw_local_irq_disable(void) |
1da177e4 LT |
90 | { |
91 | __asm__ __volatile__( | |
192ef366 | 92 | "raw_local_irq_disable" |
1da177e4 LT |
93 | : /* no outputs */ |
94 | : /* no inputs */ | |
95 | : "memory"); | |
96 | } | |
97 | ||
98 | __asm__ ( | |
192ef366 | 99 | " .macro raw_local_save_flags flags \n" |
ff88f8a3 RB |
100 | " .set push \n" |
101 | " .set reorder \n" | |
41c594ab RB |
102 | #ifdef CONFIG_MIPS_MT_SMTC |
103 | " mfc0 \\flags, $2, 1 \n" | |
104 | #else | |
ff88f8a3 | 105 | " mfc0 \\flags, $12 \n" |
41c594ab | 106 | #endif |
ff88f8a3 RB |
107 | " .set pop \n" |
108 | " .endm \n"); | |
1da177e4 | 109 | |
192ef366 | 110 | #define raw_local_save_flags(x) \ |
1da177e4 | 111 | __asm__ __volatile__( \ |
192ef366 | 112 | "raw_local_save_flags %0" \ |
1da177e4 LT |
113 | : "=r" (x)) |
114 | ||
115 | __asm__ ( | |
192ef366 | 116 | " .macro raw_local_irq_save result \n" |
ff88f8a3 RB |
117 | " .set push \n" |
118 | " .set reorder \n" | |
119 | " .set noat \n" | |
41c594ab RB |
120 | #ifdef CONFIG_MIPS_MT_SMTC |
121 | " mfc0 \\result, $2, 1 \n" | |
122 | " ori $1, \\result, 0x400 \n" | |
123 | " .set noreorder \n" | |
124 | " mtc0 $1, $2, 1 \n" | |
125 | " andi \\result, \\result, 0x400 \n" | |
126 | #elif defined(CONFIG_CPU_MIPSR2) | |
ff88f8a3 | 127 | " di \\result \n" |
15265251 | 128 | " andi \\result, 1 \n" |
ff88f8a3 RB |
129 | #else |
130 | " mfc0 \\result, $12 \n" | |
c226f260 AN |
131 | " ori $1, \\result, 0x1f \n" |
132 | " xori $1, 0x1f \n" | |
ff88f8a3 RB |
133 | " .set noreorder \n" |
134 | " mtc0 $1, $12 \n" | |
135 | #endif | |
136 | " irq_disable_hazard \n" | |
137 | " .set pop \n" | |
138 | " .endm \n"); | |
1da177e4 | 139 | |
192ef366 | 140 | #define raw_local_irq_save(x) \ |
1da177e4 | 141 | __asm__ __volatile__( \ |
192ef366 | 142 | "raw_local_irq_save\t%0" \ |
1da177e4 LT |
143 | : "=r" (x) \ |
144 | : /* no inputs */ \ | |
145 | : "memory") | |
146 | ||
147 | __asm__ ( | |
192ef366 | 148 | " .macro raw_local_irq_restore flags \n" |
2e66fe24 | 149 | " .set push \n" |
ff88f8a3 RB |
150 | " .set noreorder \n" |
151 | " .set noat \n" | |
41c594ab RB |
152 | #ifdef CONFIG_MIPS_MT_SMTC |
153 | "mfc0 $1, $2, 1 \n" | |
154 | "andi \\flags, 0x400 \n" | |
155 | "ori $1, 0x400 \n" | |
156 | "xori $1, 0x400 \n" | |
157 | "or \\flags, $1 \n" | |
158 | "mtc0 \\flags, $2, 1 \n" | |
159 | #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) | |
ff88f8a3 RB |
160 | /* |
161 | * Slow, but doesn't suffer from a relativly unlikely race | |
162 | * condition we're having since days 1. | |
163 | */ | |
164 | " beqz \\flags, 1f \n" | |
165 | " di \n" | |
166 | " ei \n" | |
167 | "1: \n" | |
ec917c2c | 168 | #elif defined(CONFIG_CPU_MIPSR2) |
ff88f8a3 RB |
169 | /* |
170 | * Fast, dangerous. Life is fun, life is good. | |
171 | */ | |
172 | " mfc0 $1, $12 \n" | |
173 | " ins $1, \\flags, 0, 1 \n" | |
174 | " mtc0 $1, $12 \n" | |
175 | #else | |
176 | " mfc0 $1, $12 \n" | |
177 | " andi \\flags, 1 \n" | |
c226f260 AN |
178 | " ori $1, 0x1f \n" |
179 | " xori $1, 0x1f \n" | |
ff88f8a3 RB |
180 | " or \\flags, $1 \n" |
181 | " mtc0 \\flags, $12 \n" | |
182 | #endif | |
183 | " irq_disable_hazard \n" | |
2e66fe24 | 184 | " .set pop \n" |
ff88f8a3 | 185 | " .endm \n"); |
1da177e4 | 186 | |
192ef366 | 187 | #define raw_local_irq_restore(flags) \ |
1da177e4 LT |
188 | do { \ |
189 | unsigned long __tmp1; \ | |
190 | \ | |
191 | __asm__ __volatile__( \ | |
192ef366 | 192 | "raw_local_irq_restore\t%0" \ |
1da177e4 LT |
193 | : "=r" (__tmp1) \ |
194 | : "0" (flags) \ | |
195 | : "memory"); \ | |
196 | } while(0) | |
197 | ||
192ef366 | 198 | static inline int raw_irqs_disabled_flags(unsigned long flags) |
41c594ab RB |
199 | { |
200 | #ifdef CONFIG_MIPS_MT_SMTC | |
201 | /* | |
202 | * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU | |
203 | */ | |
192ef366 | 204 | return flags & 0x400; |
41c594ab | 205 | #else |
41c594ab RB |
206 | return !(flags & 1); |
207 | #endif | |
208 | } | |
1da177e4 | 209 | |
192ef366 RB |
210 | #endif |
211 | ||
212 | /* | |
213 | * Do the CPU's IRQ-state tracing from assembly code. | |
214 | */ | |
215 | #ifdef CONFIG_TRACE_IRQFLAGS | |
216 | # define TRACE_IRQS_ON \ | |
217 | jal trace_hardirqs_on | |
218 | # define TRACE_IRQS_OFF \ | |
219 | jal trace_hardirqs_off | |
220 | #else | |
221 | # define TRACE_IRQS_ON | |
222 | # define TRACE_IRQS_OFF | |
223 | #endif | |
224 | ||
225 | #endif /* _ASM_IRQFLAGS_H */ |