projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* ********************************************************************* |
| 2 | * SB1250 Board Support Package | |
| 42a3b4f2 | 3 | * |
| 1da177e4 | 4 | * Generic Bus Constants File: sb1250_genbus.h |
| 42a3b4f2 RB |
5 | * |
| 6 | * This module contains constants and macros useful for | |
| 1da177e4 | 7 | * manipulating the SB1250's Generic Bus interface |
| 42a3b4f2 | 8 | * |
| 1da177e4 | 9 | * SB1250 specification level: User's manual 1/02/02 |
| 42a3b4f2 | 10 | * |
| 1da177e4 | 11 | * Author: Mitch Lichtenberg |
| 42a3b4f2 RB |
12 | * |
| 13 | ********************************************************************* | |
| 1da177e4 LT |
14 | * |
| 15 | * Copyright 2000,2001,2002,2003 | |
| 16 | * Broadcom Corporation. All rights reserved. | |
| 42a3b4f2 RB |
17 | * |
| 18 | * This program is free software; you can redistribute it and/or | |
| 19 | * modify it under the terms of the GNU General Public License as | |
| 20 | * published by the Free Software Foundation; either version 2 of | |
| 1da177e4 LT |
21 | * the License, or (at your option) any later version. |
| 22 | * | |
| 23 | * This program is distributed in the hope that it will be useful, | |
| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 26 | * GNU General Public License for more details. | |
| 27 | * | |
| 28 | * You should have received a copy of the GNU General Public License | |
| 29 | * along with this program; if not, write to the Free Software | |
| 42a3b4f2 | 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 1da177e4 LT |
31 | * MA 02111-1307 USA |
| 32 | ********************************************************************* */ | |
| 33 | ||
| 34 | ||
| 35 | #ifndef _SB1250_GENBUS_H | |
| 36 | #define _SB1250_GENBUS_H | |
| 37 | ||
| 38 | #include "sb1250_defs.h" | |
| 39 | ||
| 40 | /* | |
| 41 | * Generic Bus Region Configuration Registers (Table 11-4) | |
| 42 | */ | |
| 43 | ||
| 44 | #define S_IO_RDY_ACTIVE 0 | |
| 45 | #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) | |
| 46 | ||
| 47 | #define S_IO_ENA_RDY 1 | |
| 48 | #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) | |
| 49 | ||
| 50 | #define S_IO_WIDTH_SEL 2 | |
| 51 | #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) | |
| 52 | #define K_IO_WIDTH_SEL_1 0 | |
| 53 | #define K_IO_WIDTH_SEL_2 1 | |
| 54 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 55 | #define K_IO_WIDTH_SEL_1L 2 | |
| 56 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 57 | #define K_IO_WIDTH_SEL_4 3 | |
| 58 | #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) | |
| 59 | #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) | |
| 60 | ||
| 61 | #define S_IO_PARITY_ENA 4 | |
| 62 | #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) | |
| 63 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 64 | #define S_IO_BURST_EN 5 | |
| 65 | #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) | |
| 66 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 67 | #define S_IO_PARITY_ODD 6 | |
| 68 | #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) | |
| 69 | #define S_IO_NONMUX 7 | |
| 70 | #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) | |
| 71 | ||
| 72 | #define S_IO_TIMEOUT 8 | |
| 73 | #define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) | |
| 74 | #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) | |
| 75 | #define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) | |
| 76 | ||
| 77 | /* | |
| 78 | * Generic Bus Region Size register (Table 11-5) | |
| 79 | */ | |
| 80 | ||
| 81 | #define S_IO_MULT_SIZE 0 | |
| 82 | #define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) | |
| 83 | #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) | |
| 84 | #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) | |
| 85 | ||
| 86 | #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ | |
| 87 | ||
| 88 | /* | |
| 89 | * Generic Bus Region Address (Table 11-6) | |
| 90 | */ | |
| 91 | ||
| 92 | #define S_IO_START_ADDR 0 | |
| 93 | #define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) | |
| 94 | #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) | |
| 95 | #define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) | |
| 96 | ||
| 97 | #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ | |
| 98 | ||
| 99 | /* | |
| 100 | * Generic Bus Region 0 Timing Registers (Table 11-7) | |
| 101 | */ | |
| 102 | ||
| 103 | #define S_IO_ALE_WIDTH 0 | |
| 104 | #define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) | |
| 105 | #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) | |
| 106 | #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) | |
| 107 | ||
| 108 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 109 | #define M_IO_EARLY_CS _SB_MAKEMASK1(3) | |
| 110 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 111 | ||
| 112 | #define S_IO_ALE_TO_CS 4 | |
| 113 | #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) | |
| 114 | #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) | |
| 115 | #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) | |
| 116 | ||
| 117 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 118 | #define S_IO_BURST_WIDTH _SB_MAKE64(6) | |
| 119 | #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) | |
| 120 | #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) | |
| 121 | #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) | |
| 122 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 123 | ||
| 124 | #define S_IO_CS_WIDTH 8 | |
| 125 | #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) | |
| 126 | #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) | |
| 127 | #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) | |
| 128 | ||
| 129 | #define S_IO_RDY_SMPLE 13 | |
| 130 | #define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) | |
| 131 | #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) | |
| 132 | #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) | |
| 133 | ||
| 134 | ||
| 135 | /* | |
| 136 | * Generic Bus Timing 1 Registers (Table 11-8) | |
| 137 | */ | |
| 138 | ||
| 139 | #define S_IO_ALE_TO_WRITE 0 | |
| 140 | #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) | |
| 141 | #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) | |
| 142 | #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) | |
| 143 | ||
| 144 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 145 | #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) | |
| 146 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 147 | ||
| 148 | #define S_IO_WRITE_WIDTH 4 | |
| 149 | #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) | |
| 150 | #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) | |
| 151 | #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) | |
| 152 | ||
| 153 | #define S_IO_IDLE_CYCLE 8 | |
| 154 | #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) | |
| 155 | #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) | |
| 156 | #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) | |
| 157 | ||
| 158 | #define S_IO_OE_TO_CS 12 | |
| 159 | #define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) | |
| 160 | #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) | |
| 161 | #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) | |
| 162 | ||
| 163 | #define S_IO_CS_TO_OE 14 | |
| 164 | #define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) | |
| 165 | #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) | |
| 166 | #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) | |
| 167 | ||
| 168 | /* | |
| 169 | * Generic Bus Interrupt Status Register (Table 11-9) | |
| 170 | */ | |
| 171 | ||
| 172 | #define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) | |
| 173 | #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) | |
| 174 | #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) | |
| 175 | #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) | |
| 176 | #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) | |
| 177 | #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) | |
| 178 | #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) | |
| 179 | #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) | |
| 180 | #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) | |
| 181 | ||
| 182 | #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) | |
| 183 | #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) | |
| 184 | #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) | |
| 185 | #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) | |
| 186 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 187 | #define M_IO_COH_ERR _SB_MAKEMASK1(14) | |
| 188 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 189 | ||
| 190 | /* | |
| 191 | * PCMCIA configuration register (Table 12-6) | |
| 192 | */ | |
| 193 | ||
| 194 | #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) | |
| 195 | #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) | |
| 196 | #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) | |
| 197 | #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) | |
| 198 | #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) | |
| 199 | #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) | |
| 200 | #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) | |
| 201 | #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) | |
| 202 | #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) | |
| 203 | #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) | |
| 204 | ||
| 205 | /* | |
| 206 | * PCMCIA status register (Table 12-7) | |
| 207 | */ | |
| 208 | ||
| 209 | #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) | |
| 210 | #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) | |
| 211 | #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) | |
| 212 | #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) | |
| 213 | #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) | |
| 214 | #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) | |
| 215 | #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) | |
| 216 | #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) | |
| 217 | #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) | |
| 218 | #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) | |
| 219 | #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) | |
| 220 | ||
| 221 | /* | |
| 222 | * GPIO Interrupt Type Register (table 13-3) | |
| 223 | */ | |
| 224 | ||
| 225 | #define K_GPIO_INTR_DISABLE 0 | |
| 226 | #define K_GPIO_INTR_EDGE 1 | |
| 227 | #define K_GPIO_INTR_LEVEL 2 | |
| 228 | #define K_GPIO_INTR_SPLIT 3 | |
| 229 | ||
| 230 | #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) | |
| 231 | #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) | |
| 232 | #define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) | |
| 233 | #define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) | |
| 234 | ||
| 235 | #define S_GPIO_INTR_TYPE0 0 | |
| 236 | #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) | |
| 237 | #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) | |
| 238 | #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) | |
| 239 | ||
| 240 | #define S_GPIO_INTR_TYPE2 2 | |
| 241 | #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) | |
| 242 | #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) | |
| 243 | #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) | |
| 244 | ||
| 245 | #define S_GPIO_INTR_TYPE4 4 | |
| 246 | #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) | |
| 247 | #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) | |
| 248 | #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) | |
| 249 | ||
| 250 | #define S_GPIO_INTR_TYPE6 6 | |
| 251 | #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) | |
| 252 | #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) | |
| 253 | #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) | |
| 254 | ||
| 255 | #define S_GPIO_INTR_TYPE8 8 | |
| 256 | #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) | |
| 257 | #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) | |
| 258 | #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) | |
| 259 | ||
| 260 | #define S_GPIO_INTR_TYPE10 10 | |
| 261 | #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) | |
| 262 | #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) | |
| 263 | #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) | |
| 264 | ||
| 265 | #define S_GPIO_INTR_TYPE12 12 | |
| 266 | #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) | |
| 267 | #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) | |
| 268 | #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) | |
| 269 | ||
| 270 | #define S_GPIO_INTR_TYPE14 14 | |
| 271 | #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) | |
| 272 | #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) | |
| 273 | #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) | |
| 274 | ||
| 275 | ||
| 276 | #endif |