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1da177e4 LT |
1 | /* ********************************************************************* |
2 | * SB1250 Board Support Package | |
3 | * | |
4 | * MAC constants and macros File: sb1250_mac.h | |
5 | * | |
6 | * This module contains constants and macros for the SB1250's | |
7 | * ethernet controllers. | |
8 | * | |
9 | * SB1250 specification level: User's manual 1/02/02 | |
10 | * | |
11 | * Author: Mitch Lichtenberg | |
12 | * | |
13 | ********************************************************************* | |
14 | * | |
15 | * Copyright 2000,2001,2002,2003 | |
16 | * Broadcom Corporation. All rights reserved. | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License as | |
20 | * published by the Free Software Foundation; either version 2 of | |
21 | * the License, or (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
31 | * MA 02111-1307 USA | |
32 | ********************************************************************* */ | |
33 | ||
34 | ||
35 | #ifndef _SB1250_MAC_H | |
36 | #define _SB1250_MAC_H | |
37 | ||
38 | #include "sb1250_defs.h" | |
39 | ||
40 | /* ********************************************************************* | |
41 | * Ethernet MAC Registers | |
42 | ********************************************************************* */ | |
43 | ||
44 | /* | |
45 | * MAC Configuration Register (Table 9-13) | |
46 | * Register: MAC_CFG_0 | |
47 | * Register: MAC_CFG_1 | |
48 | * Register: MAC_CFG_2 | |
49 | */ | |
50 | ||
51 | ||
52 | #define M_MAC_RESERVED0 _SB_MAKEMASK1(0) | |
53 | #define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) | |
54 | #define M_MAC_RETRY_EN _SB_MAKEMASK1(2) | |
55 | #define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) | |
56 | #define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) | |
57 | #define M_MAC_BURST_EN _SB_MAKEMASK1(5) | |
58 | ||
59 | #define S_MAC_TX_PAUSE _SB_MAKE64(6) | |
60 | #define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) | |
61 | #define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) | |
62 | ||
63 | #define K_MAC_TX_PAUSE_CNT_512 0 | |
64 | #define K_MAC_TX_PAUSE_CNT_1K 1 | |
65 | #define K_MAC_TX_PAUSE_CNT_2K 2 | |
66 | #define K_MAC_TX_PAUSE_CNT_4K 3 | |
67 | #define K_MAC_TX_PAUSE_CNT_8K 4 | |
68 | #define K_MAC_TX_PAUSE_CNT_16K 5 | |
69 | #define K_MAC_TX_PAUSE_CNT_32K 6 | |
70 | #define K_MAC_TX_PAUSE_CNT_64K 7 | |
71 | ||
72 | #define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) | |
73 | #define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) | |
74 | #define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) | |
75 | #define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) | |
76 | #define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) | |
77 | #define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) | |
78 | #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) | |
79 | #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) | |
80 | ||
81 | #define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) | |
82 | ||
83 | #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) | |
84 | #define M_MAC_RESERVED2 _SB_MAKEMASK1(18) | |
85 | #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) | |
86 | #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) | |
87 | #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) | |
88 | #define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) | |
89 | #define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) | |
90 | #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) | |
91 | #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) | |
92 | ||
93 | #define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) | |
94 | ||
95 | #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) | |
96 | #define M_MAC_HDX_EN _SB_MAKEMASK1(33) | |
97 | ||
98 | #define S_MAC_SPEED_SEL _SB_MAKE64(34) | |
99 | #define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) | |
100 | #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) | |
101 | #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) | |
102 | ||
103 | #define K_MAC_SPEED_SEL_10MBPS 0 | |
104 | #define K_MAC_SPEED_SEL_100MBPS 1 | |
105 | #define K_MAC_SPEED_SEL_1000MBPS 2 | |
106 | #define K_MAC_SPEED_SEL_RESERVED 3 | |
107 | ||
108 | #define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) | |
109 | #define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) | |
110 | #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) | |
111 | #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) | |
112 | ||
113 | #define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) | |
114 | #define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) | |
115 | #define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) | |
116 | #define M_MAC_SS_EN _SB_MAKEMASK1(39) | |
117 | ||
118 | #define S_MAC_BYPASS_CFG _SB_MAKE64(40) | |
119 | #define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) | |
120 | #define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) | |
121 | #define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) | |
122 | ||
123 | #define K_MAC_BYPASS_GMII 0 | |
124 | #define K_MAC_BYPASS_ENCODED 1 | |
125 | #define K_MAC_BYPASS_SOP 2 | |
126 | #define K_MAC_BYPASS_EOP 3 | |
127 | ||
128 | #define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) | |
129 | #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) | |
130 | ||
131 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
132 | #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) | |
133 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
134 | ||
135 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
136 | #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) | |
137 | #endif /* 1250 PASS3 || 112x PASS1 */ | |
138 | ||
139 | #define S_MAC_BYPASS_IFG _SB_MAKE64(46) | |
140 | #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) | |
141 | #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) | |
142 | #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) | |
143 | ||
144 | #define K_MAC_FC_CMD_DISABLED 0 | |
145 | #define K_MAC_FC_CMD_ENABLED 1 | |
146 | #define K_MAC_FC_CMD_ENAB_FALSECARR 2 | |
147 | ||
148 | #define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) | |
149 | #define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) | |
150 | #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) | |
151 | ||
152 | #define M_MAC_FC_SEL _SB_MAKEMASK1(54) | |
153 | ||
154 | #define S_MAC_FC_CMD _SB_MAKE64(55) | |
155 | #define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) | |
156 | #define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) | |
157 | #define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) | |
158 | ||
159 | #define S_MAC_RX_CH_SEL _SB_MAKE64(57) | |
160 | #define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) | |
161 | #define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) | |
162 | #define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) | |
163 | ||
164 | ||
165 | /* | |
166 | * MAC Enable Registers | |
167 | * Register: MAC_ENABLE_0 | |
168 | * Register: MAC_ENABLE_1 | |
169 | * Register: MAC_ENABLE_2 | |
170 | */ | |
171 | ||
172 | #define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) | |
173 | #define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) | |
174 | #define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) | |
175 | #define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) | |
176 | ||
177 | #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) | |
178 | ||
179 | #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) | |
180 | #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) | |
181 | #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) | |
182 | #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) | |
183 | ||
184 | /* | |
185 | * MAC DMA Control Register | |
186 | * Register: MAC_TXD_CTL_0 | |
187 | * Register: MAC_TXD_CTL_1 | |
188 | * Register: MAC_TXD_CTL_2 | |
189 | */ | |
190 | ||
191 | #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) | |
192 | #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) | |
193 | #define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) | |
194 | #define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) | |
195 | ||
196 | #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) | |
197 | #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) | |
198 | #define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) | |
199 | #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) | |
200 | ||
201 | /* | |
202 | * MAC Fifo Threshhold registers (Table 9-14) | |
203 | * Register: MAC_THRSH_CFG_0 | |
204 | * Register: MAC_THRSH_CFG_1 | |
205 | * Register: MAC_THRSH_CFG_2 | |
206 | */ | |
207 | ||
208 | #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) | |
209 | #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) | |
210 | /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ | |
211 | /* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ | |
212 | #endif /* up to 1250 PASS1 */ | |
213 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
214 | #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) | |
215 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
216 | #define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) | |
217 | #define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) | |
218 | ||
219 | #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) | |
220 | #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) | |
221 | /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ | |
222 | /* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ | |
223 | #endif /* up to 1250 PASS1 */ | |
224 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
225 | #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) | |
226 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
227 | #define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) | |
228 | #define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) | |
229 | ||
230 | #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) | |
231 | #define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) | |
232 | #define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) | |
233 | #define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) | |
234 | ||
235 | #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) | |
236 | #define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) | |
237 | #define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) | |
238 | #define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) | |
239 | ||
240 | #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) | |
241 | #define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) | |
242 | #define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) | |
243 | #define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) | |
244 | ||
245 | #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) | |
246 | #define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) | |
247 | #define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) | |
248 | #define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) | |
249 | ||
250 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
251 | #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) | |
252 | #define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) | |
253 | #define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) | |
254 | #define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) | |
255 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
256 | ||
257 | /* | |
258 | * MAC Frame Configuration Registers (Table 9-15) | |
259 | * Register: MAC_FRAME_CFG_0 | |
260 | * Register: MAC_FRAME_CFG_1 | |
261 | * Register: MAC_FRAME_CFG_2 | |
262 | */ | |
263 | ||
264 | /* XXXCGD: ??? Unused in pass2? */ | |
265 | #define S_MAC_IFG_RX _SB_MAKE64(0) | |
266 | #define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) | |
267 | #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) | |
268 | #define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) | |
269 | ||
270 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
271 | #define S_MAC_PRE_LEN _SB_MAKE64(0) | |
272 | #define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) | |
273 | #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) | |
274 | #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) | |
275 | #endif /* 1250 PASS3 || 112x PASS1 */ | |
276 | ||
277 | #define S_MAC_IFG_TX _SB_MAKE64(6) | |
278 | #define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) | |
279 | #define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) | |
280 | #define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) | |
281 | ||
282 | #define S_MAC_IFG_THRSH _SB_MAKE64(12) | |
283 | #define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) | |
284 | #define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) | |
285 | #define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) | |
286 | ||
287 | #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) | |
288 | #define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) | |
289 | #define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) | |
290 | #define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) | |
291 | ||
292 | #define S_MAC_LFSR_SEED _SB_MAKE64(22) | |
293 | #define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) | |
294 | #define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) | |
295 | #define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) | |
296 | ||
297 | #define S_MAC_SLOT_SIZE _SB_MAKE64(30) | |
298 | #define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) | |
299 | #define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) | |
300 | #define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) | |
301 | ||
302 | #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) | |
303 | #define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) | |
304 | #define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) | |
305 | #define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) | |
306 | ||
307 | #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) | |
308 | #define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) | |
309 | #define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) | |
310 | #define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) | |
311 | ||
312 | /* | |
313 | * These constants are used to configure the fields within the Frame | |
314 | * Configuration Register. | |
315 | */ | |
316 | ||
317 | #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ | |
318 | #define K_MAC_IFG_RX_100 _SB_MAKE64(0) | |
319 | #define K_MAC_IFG_RX_1000 _SB_MAKE64(0) | |
320 | ||
321 | #define K_MAC_IFG_TX_10 _SB_MAKE64(20) | |
322 | #define K_MAC_IFG_TX_100 _SB_MAKE64(20) | |
323 | #define K_MAC_IFG_TX_1000 _SB_MAKE64(8) | |
324 | ||
325 | #define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) | |
326 | #define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) | |
327 | #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) | |
328 | ||
329 | #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) | |
330 | #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) | |
331 | #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) | |
332 | ||
333 | #define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) | |
334 | #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) | |
335 | #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) | |
336 | ||
337 | #define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) | |
338 | #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) | |
339 | #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) | |
340 | ||
341 | #define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) | |
342 | #define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) | |
343 | #define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) | |
344 | ||
345 | #define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) | |
346 | #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) | |
347 | #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) | |
348 | ||
349 | #define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) | |
350 | #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) | |
351 | #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) | |
352 | #define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) | |
353 | ||
354 | #define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) | |
355 | #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) | |
356 | #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) | |
357 | #define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) | |
358 | ||
359 | /* | |
360 | * MAC VLAN Tag Registers (Table 9-16) | |
361 | * Register: MAC_VLANTAG_0 | |
362 | * Register: MAC_VLANTAG_1 | |
363 | * Register: MAC_VLANTAG_2 | |
364 | */ | |
365 | ||
366 | #define S_MAC_VLAN_TAG _SB_MAKE64(0) | |
367 | #define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) | |
368 | #define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) | |
369 | #define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) | |
370 | ||
371 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
372 | #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) | |
373 | #define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) | |
374 | #define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) | |
375 | #define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) | |
376 | ||
377 | #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) | |
378 | #define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) | |
379 | #define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) | |
380 | #define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) | |
381 | ||
382 | #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) | |
383 | #endif /* 1250 PASS3 || 112x PASS1 */ | |
384 | ||
385 | /* | |
386 | * MAC Status Registers (Table 9-17) | |
387 | * Also used for the MAC Interrupt Mask Register (Table 9-18) | |
388 | * Register: MAC_STATUS_0 | |
389 | * Register: MAC_STATUS_1 | |
390 | * Register: MAC_STATUS_2 | |
391 | * Register: MAC_INT_MASK_0 | |
392 | * Register: MAC_INT_MASK_1 | |
393 | * Register: MAC_INT_MASK_2 | |
394 | */ | |
395 | ||
396 | /* | |
397 | * Use these constants to shift the appropriate channel | |
398 | * into the CH0 position so the same tests can be used | |
399 | * on each channel. | |
400 | */ | |
401 | ||
402 | #define S_MAC_RX_CH0 _SB_MAKE64(0) | |
403 | #define S_MAC_RX_CH1 _SB_MAKE64(8) | |
404 | #define S_MAC_TX_CH0 _SB_MAKE64(16) | |
405 | #define S_MAC_TX_CH1 _SB_MAKE64(24) | |
406 | ||
407 | #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ | |
408 | #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ | |
409 | ||
410 | /* | |
411 | * These are the same as RX channel 0. The idea here | |
412 | * is that you'll use one of the "S_" things above | |
413 | * and pass just the six bits to a DMA-channel-specific ISR | |
414 | */ | |
415 | #define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) | |
416 | #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) | |
417 | #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) | |
418 | #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) | |
419 | #define M_MAC_INT_HWM _SB_MAKEMASK1(3) | |
420 | #define M_MAC_INT_LWM _SB_MAKEMASK1(4) | |
421 | #define M_MAC_INT_DSCR _SB_MAKEMASK1(5) | |
422 | #define M_MAC_INT_ERR _SB_MAKEMASK1(6) | |
423 | #define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ | |
424 | #define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ | |
425 | ||
426 | /* | |
427 | * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see | |
428 | * also DMA_TX/DMA_RX in sb_regs.h). | |
429 | */ | |
430 | #define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) | |
431 | ||
432 | #define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
433 | #define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
434 | #define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
435 | #define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
436 | #define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
437 | #define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
438 | #define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
439 | #define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
440 | #define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
441 | #define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) | |
442 | #define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) | |
443 | ||
444 | ||
445 | #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) | |
446 | #define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) | |
447 | #define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) | |
448 | #define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) | |
449 | #define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) | |
450 | #define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) | |
451 | #define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) | |
452 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
453 | #define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ | |
454 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
455 | ||
456 | #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) | |
457 | #define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) | |
458 | #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) | |
459 | #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) | |
460 | ||
461 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
462 | #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) | |
463 | #endif /* 1250 PASS3 || 112x PASS1 */ | |
464 | ||
465 | /* | |
466 | * MAC Fifo Pointer Registers (Table 9-19) [Debug register] | |
467 | * Register: MAC_FIFO_PTRS_0 | |
468 | * Register: MAC_FIFO_PTRS_1 | |
469 | * Register: MAC_FIFO_PTRS_2 | |
470 | */ | |
471 | ||
472 | #define S_MAC_TX_WRPTR _SB_MAKE64(0) | |
473 | #define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) | |
474 | #define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) | |
475 | #define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) | |
476 | ||
477 | #define S_MAC_TX_RDPTR _SB_MAKE64(8) | |
478 | #define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) | |
479 | #define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) | |
480 | #define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) | |
481 | ||
482 | #define S_MAC_RX_WRPTR _SB_MAKE64(16) | |
483 | #define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) | |
484 | #define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) | |
485 | #define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) | |
486 | ||
487 | #define S_MAC_RX_RDPTR _SB_MAKE64(24) | |
488 | #define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) | |
489 | #define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) | |
490 | #define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) | |
491 | ||
492 | /* | |
493 | * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] | |
494 | * Register: MAC_EOPCNT_0 | |
495 | * Register: MAC_EOPCNT_1 | |
496 | * Register: MAC_EOPCNT_2 | |
497 | */ | |
498 | ||
499 | #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) | |
500 | #define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) | |
501 | #define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) | |
502 | #define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) | |
503 | ||
504 | #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) | |
505 | #define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) | |
506 | #define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) | |
507 | #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) | |
508 | ||
509 | /* | |
510 | * MAC Recieve Address Filter Exact Match Registers (Table 9-21) | |
511 | * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 | |
512 | * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 | |
513 | * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 | |
514 | */ | |
515 | ||
516 | /* No bitfields */ | |
517 | ||
518 | /* | |
519 | * MAC Receive Address Filter Mask Registers | |
520 | * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 | |
521 | * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 | |
522 | * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 | |
523 | */ | |
524 | ||
525 | /* No bitfields */ | |
526 | ||
527 | /* | |
528 | * MAC Recieve Address Filter Hash Match Registers (Table 9-22) | |
529 | * Registers: MAC_HASH0_0 through MAC_HASH7_0 | |
530 | * Registers: MAC_HASH0_1 through MAC_HASH7_1 | |
531 | * Registers: MAC_HASH0_2 through MAC_HASH7_2 | |
532 | */ | |
533 | ||
534 | /* No bitfields */ | |
535 | ||
536 | /* | |
537 | * MAC Transmit Source Address Registers (Table 9-23) | |
538 | * Register: MAC_ETHERNET_ADDR_0 | |
539 | * Register: MAC_ETHERNET_ADDR_1 | |
540 | * Register: MAC_ETHERNET_ADDR_2 | |
541 | */ | |
542 | ||
543 | /* No bitfields */ | |
544 | ||
545 | /* | |
546 | * MAC Packet Type Configuration Register | |
547 | * Register: MAC_TYPE_CFG_0 | |
548 | * Register: MAC_TYPE_CFG_1 | |
549 | * Register: MAC_TYPE_CFG_2 | |
550 | */ | |
551 | ||
552 | #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) | |
553 | ||
554 | #define S_TYPECFG_TYPE0 _SB_MAKE64(0) | |
555 | #define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) | |
556 | #define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) | |
557 | #define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) | |
558 | ||
559 | #define S_TYPECFG_TYPE1 _SB_MAKE64(0) | |
560 | #define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) | |
561 | #define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) | |
562 | #define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) | |
563 | ||
564 | #define S_TYPECFG_TYPE2 _SB_MAKE64(0) | |
565 | #define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) | |
566 | #define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) | |
567 | #define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) | |
568 | ||
569 | #define S_TYPECFG_TYPE3 _SB_MAKE64(0) | |
570 | #define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) | |
571 | #define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) | |
572 | #define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) | |
573 | ||
574 | /* | |
575 | * MAC Receive Address Filter Control Registers (Table 9-24) | |
576 | * Register: MAC_ADFILTER_CFG_0 | |
577 | * Register: MAC_ADFILTER_CFG_1 | |
578 | * Register: MAC_ADFILTER_CFG_2 | |
579 | */ | |
580 | ||
581 | #define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) | |
582 | #define M_MAC_UCAST_EN _SB_MAKEMASK1(1) | |
583 | #define M_MAC_UCAST_INV _SB_MAKEMASK1(2) | |
584 | #define M_MAC_MCAST_EN _SB_MAKEMASK1(3) | |
585 | #define M_MAC_MCAST_INV _SB_MAKEMASK1(4) | |
586 | #define M_MAC_BCAST_EN _SB_MAKEMASK1(5) | |
587 | #define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) | |
588 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
589 | #define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) | |
590 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
591 | ||
592 | #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) | |
593 | #define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) | |
594 | #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) | |
595 | #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) | |
596 | ||
597 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
598 | #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) | |
599 | #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) | |
600 | #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) | |
601 | #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) | |
602 | ||
603 | #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) | |
604 | #define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) | |
605 | #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) | |
606 | #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) | |
607 | ||
608 | #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) | |
609 | #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) | |
610 | ||
611 | #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) | |
612 | #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) | |
613 | #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) | |
614 | #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) | |
615 | #endif /* 1250 PASS3 || 112x PASS1 */ | |
616 | ||
617 | /* | |
618 | * MAC Receive Channel Select Registers (Table 9-25) | |
619 | */ | |
620 | ||
621 | /* no bitfields */ | |
622 | ||
623 | /* | |
624 | * MAC MII Management Interface Registers (Table 9-26) | |
625 | * Register: MAC_MDIO_0 | |
626 | * Register: MAC_MDIO_1 | |
627 | * Register: MAC_MDIO_2 | |
628 | */ | |
629 | ||
630 | #define S_MAC_MDC 0 | |
631 | #define S_MAC_MDIO_DIR 1 | |
632 | #define S_MAC_MDIO_OUT 2 | |
633 | #define S_MAC_GENC 3 | |
634 | #define S_MAC_MDIO_IN 4 | |
635 | ||
636 | #define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) | |
637 | #define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) | |
638 | #define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) | |
639 | #define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) | |
640 | #define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) | |
641 | #define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) | |
642 | ||
643 | #endif |