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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle | |
7 | * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. | |
8 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
9 | */ | |
10 | #ifndef _ASM_STACKFRAME_H | |
11 | #define _ASM_STACKFRAME_H | |
12 | ||
1da177e4 LT |
13 | #include <linux/threads.h> |
14 | ||
15 | #include <asm/asm.h> | |
41c594ab | 16 | #include <asm/asmmacro.h> |
1da177e4 | 17 | #include <asm/mipsregs.h> |
048eb582 | 18 | #include <asm/asm-offsets.h> |
1da177e4 | 19 | |
41c594ab RB |
20 | #ifdef CONFIG_MIPS_MT_SMTC |
21 | #include <asm/mipsmtregs.h> | |
22 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
23 | ||
1da177e4 LT |
24 | .macro SAVE_AT |
25 | .set push | |
26 | .set noat | |
27 | LONG_S $1, PT_R1(sp) | |
28 | .set pop | |
29 | .endm | |
30 | ||
31 | .macro SAVE_TEMP | |
32 | mfhi v1 | |
875d43e7 | 33 | #ifdef CONFIG_32BIT |
1da177e4 LT |
34 | LONG_S $8, PT_R8(sp) |
35 | LONG_S $9, PT_R9(sp) | |
36 | #endif | |
37 | LONG_S v1, PT_HI(sp) | |
38 | mflo v1 | |
39 | LONG_S $10, PT_R10(sp) | |
40 | LONG_S $11, PT_R11(sp) | |
41 | LONG_S v1, PT_LO(sp) | |
42 | LONG_S $12, PT_R12(sp) | |
43 | LONG_S $13, PT_R13(sp) | |
44 | LONG_S $14, PT_R14(sp) | |
45 | LONG_S $15, PT_R15(sp) | |
46 | LONG_S $24, PT_R24(sp) | |
47 | .endm | |
48 | ||
49 | .macro SAVE_STATIC | |
50 | LONG_S $16, PT_R16(sp) | |
51 | LONG_S $17, PT_R17(sp) | |
52 | LONG_S $18, PT_R18(sp) | |
53 | LONG_S $19, PT_R19(sp) | |
54 | LONG_S $20, PT_R20(sp) | |
55 | LONG_S $21, PT_R21(sp) | |
56 | LONG_S $22, PT_R22(sp) | |
57 | LONG_S $23, PT_R23(sp) | |
58 | LONG_S $30, PT_R30(sp) | |
59 | .endm | |
60 | ||
61 | #ifdef CONFIG_SMP | |
41c594ab | 62 | #ifdef CONFIG_MIPS_MT_SMTC |
9b95e629 | 63 | #define PTEBASE_SHIFT 19 /* TCBIND */ |
41c594ab | 64 | #else |
9b95e629 | 65 | #define PTEBASE_SHIFT 23 /* CONTEXT */ |
1da177e4 | 66 | #endif |
9b95e629 | 67 | .macro get_saved_sp /* SMP variation */ |
41c594ab | 68 | #ifdef CONFIG_MIPS_MT_SMTC |
9b95e629 | 69 | mfc0 k0, CP0_TCBIND |
41c594ab | 70 | #else |
9b95e629 AN |
71 | MFC0 k0, CP0_CONTEXT |
72 | #endif | |
73 | #if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) | |
74 | lui k1, %highest(kernelsp) | |
75 | daddiu k1, %higher(kernelsp) | |
76 | dsll k1, 16 | |
77 | daddiu k1, %hi(kernelsp) | |
78 | dsll k1, 16 | |
79 | #else | |
80 | lui k1, %hi(kernelsp) | |
81 | #endif | |
82 | LONG_SRL k0, PTEBASE_SHIFT | |
83 | LONG_ADDU k1, k0 | |
85b6e818 | 84 | LONG_L k1, %lo(kernelsp)(k1) |
1da177e4 LT |
85 | .endm |
86 | ||
87 | .macro set_saved_sp stackp temp temp2 | |
41c594ab RB |
88 | #ifdef CONFIG_MIPS_MT_SMTC |
89 | mfc0 \temp, CP0_TCBIND | |
41c594ab | 90 | #else |
1b3a6e97 | 91 | MFC0 \temp, CP0_CONTEXT |
1da177e4 | 92 | #endif |
9b95e629 | 93 | LONG_SRL \temp, PTEBASE_SHIFT |
9556ac2f | 94 | LONG_S \stackp, kernelsp(\temp) |
1da177e4 LT |
95 | .endm |
96 | #else | |
97 | .macro get_saved_sp /* Uniprocessor variation */ | |
9b95e629 | 98 | #if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) |
9556ac2f TS |
99 | lui k1, %highest(kernelsp) |
100 | daddiu k1, %higher(kernelsp) | |
101 | dsll k1, k1, 16 | |
102 | daddiu k1, %hi(kernelsp) | |
103 | dsll k1, k1, 16 | |
104 | #else | |
1da177e4 | 105 | lui k1, %hi(kernelsp) |
9556ac2f | 106 | #endif |
1da177e4 LT |
107 | LONG_L k1, %lo(kernelsp)(k1) |
108 | .endm | |
109 | ||
110 | .macro set_saved_sp stackp temp temp2 | |
111 | LONG_S \stackp, kernelsp | |
112 | .endm | |
113 | #endif | |
114 | ||
115 | .macro SAVE_SOME | |
116 | .set push | |
117 | .set noat | |
118 | .set reorder | |
119 | mfc0 k0, CP0_STATUS | |
120 | sll k0, 3 /* extract cu0 bit */ | |
121 | .set noreorder | |
122 | bltz k0, 8f | |
123 | move k1, sp | |
124 | .set reorder | |
125 | /* Called from user mode, new stack. */ | |
126 | get_saved_sp | |
127 | 8: move k0, sp | |
128 | PTR_SUBU sp, k1, PT_SIZE | |
129 | LONG_S k0, PT_R29(sp) | |
130 | LONG_S $3, PT_R3(sp) | |
41c594ab RB |
131 | /* |
132 | * You might think that you don't need to save $0, | |
133 | * but the FPU emulator and gdb remote debug stub | |
134 | * need it to operate correctly | |
135 | */ | |
1da177e4 LT |
136 | LONG_S $0, PT_R0(sp) |
137 | mfc0 v1, CP0_STATUS | |
138 | LONG_S $2, PT_R2(sp) | |
139 | LONG_S v1, PT_STATUS(sp) | |
41c594ab RB |
140 | #ifdef CONFIG_MIPS_MT_SMTC |
141 | /* | |
142 | * Ideally, these instructions would be shuffled in | |
143 | * to cover the pipeline delay. | |
144 | */ | |
145 | .set mips32 | |
146 | mfc0 v1, CP0_TCSTATUS | |
147 | .set mips0 | |
148 | LONG_S v1, PT_TCSTATUS(sp) | |
149 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
150 | LONG_S $4, PT_R4(sp) |
151 | mfc0 v1, CP0_CAUSE | |
152 | LONG_S $5, PT_R5(sp) | |
153 | LONG_S v1, PT_CAUSE(sp) | |
154 | LONG_S $6, PT_R6(sp) | |
155 | MFC0 v1, CP0_EPC | |
156 | LONG_S $7, PT_R7(sp) | |
875d43e7 | 157 | #ifdef CONFIG_64BIT |
1da177e4 LT |
158 | LONG_S $8, PT_R8(sp) |
159 | LONG_S $9, PT_R9(sp) | |
160 | #endif | |
161 | LONG_S v1, PT_EPC(sp) | |
162 | LONG_S $25, PT_R25(sp) | |
163 | LONG_S $28, PT_R28(sp) | |
164 | LONG_S $31, PT_R31(sp) | |
165 | ori $28, sp, _THREAD_MASK | |
166 | xori $28, _THREAD_MASK | |
167 | .set pop | |
168 | .endm | |
169 | ||
170 | .macro SAVE_ALL | |
171 | SAVE_SOME | |
172 | SAVE_AT | |
173 | SAVE_TEMP | |
174 | SAVE_STATIC | |
175 | .endm | |
176 | ||
177 | .macro RESTORE_AT | |
178 | .set push | |
179 | .set noat | |
180 | LONG_L $1, PT_R1(sp) | |
181 | .set pop | |
182 | .endm | |
183 | ||
184 | .macro RESTORE_TEMP | |
185 | LONG_L $24, PT_LO(sp) | |
875d43e7 | 186 | #ifdef CONFIG_32BIT |
1da177e4 LT |
187 | LONG_L $8, PT_R8(sp) |
188 | LONG_L $9, PT_R9(sp) | |
189 | #endif | |
190 | mtlo $24 | |
191 | LONG_L $24, PT_HI(sp) | |
192 | LONG_L $10, PT_R10(sp) | |
193 | LONG_L $11, PT_R11(sp) | |
194 | mthi $24 | |
195 | LONG_L $12, PT_R12(sp) | |
196 | LONG_L $13, PT_R13(sp) | |
197 | LONG_L $14, PT_R14(sp) | |
198 | LONG_L $15, PT_R15(sp) | |
199 | LONG_L $24, PT_R24(sp) | |
200 | .endm | |
201 | ||
202 | .macro RESTORE_STATIC | |
203 | LONG_L $16, PT_R16(sp) | |
204 | LONG_L $17, PT_R17(sp) | |
205 | LONG_L $18, PT_R18(sp) | |
206 | LONG_L $19, PT_R19(sp) | |
207 | LONG_L $20, PT_R20(sp) | |
208 | LONG_L $21, PT_R21(sp) | |
209 | LONG_L $22, PT_R22(sp) | |
210 | LONG_L $23, PT_R23(sp) | |
211 | LONG_L $30, PT_R30(sp) | |
212 | .endm | |
213 | ||
214 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | |
215 | ||
216 | .macro RESTORE_SOME | |
217 | .set push | |
218 | .set reorder | |
219 | .set noat | |
220 | mfc0 a0, CP0_STATUS | |
221 | ori a0, 0x1f | |
222 | xori a0, 0x1f | |
223 | mtc0 a0, CP0_STATUS | |
224 | li v1, 0xff00 | |
225 | and a0, v1 | |
226 | LONG_L v0, PT_STATUS(sp) | |
227 | nor v1, $0, v1 | |
228 | and v0, v1 | |
229 | or v0, a0 | |
230 | mtc0 v0, CP0_STATUS | |
231 | LONG_L $31, PT_R31(sp) | |
232 | LONG_L $28, PT_R28(sp) | |
233 | LONG_L $25, PT_R25(sp) | |
875d43e7 | 234 | #ifdef CONFIG_64BIT |
1da177e4 LT |
235 | LONG_L $8, PT_R8(sp) |
236 | LONG_L $9, PT_R9(sp) | |
237 | #endif | |
238 | LONG_L $7, PT_R7(sp) | |
239 | LONG_L $6, PT_R6(sp) | |
240 | LONG_L $5, PT_R5(sp) | |
241 | LONG_L $4, PT_R4(sp) | |
242 | LONG_L $3, PT_R3(sp) | |
243 | LONG_L $2, PT_R2(sp) | |
244 | .set pop | |
245 | .endm | |
246 | ||
247 | .macro RESTORE_SP_AND_RET | |
248 | .set push | |
249 | .set noreorder | |
250 | LONG_L k0, PT_EPC(sp) | |
251 | LONG_L sp, PT_R29(sp) | |
252 | jr k0 | |
253 | rfe | |
254 | .set pop | |
255 | .endm | |
256 | ||
257 | #else | |
41c594ab RB |
258 | /* |
259 | * For SMTC kernel, global IE should be left set, and interrupts | |
260 | * controlled exclusively via IXMT. | |
261 | */ | |
1da177e4 | 262 | |
41c594ab RB |
263 | #ifdef CONFIG_MIPS_MT_SMTC |
264 | #define STATMASK 0x1e | |
265 | #else | |
266 | #define STATMASK 0x1f | |
267 | #endif | |
1da177e4 LT |
268 | .macro RESTORE_SOME |
269 | .set push | |
270 | .set reorder | |
271 | .set noat | |
41c594ab RB |
272 | #ifdef CONFIG_MIPS_MT_SMTC |
273 | .set mips32r2 | |
274 | /* | |
275 | * This may not really be necessary if ints are already | |
276 | * inhibited here. | |
277 | */ | |
278 | mfc0 v0, CP0_TCSTATUS | |
279 | ori v0, TCSTATUS_IXMT | |
280 | mtc0 v0, CP0_TCSTATUS | |
4277ff5e | 281 | _ehb |
41c594ab RB |
282 | DMT 5 # dmt a1 |
283 | jal mips_ihb | |
284 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 285 | mfc0 a0, CP0_STATUS |
41c594ab RB |
286 | ori a0, STATMASK |
287 | xori a0, STATMASK | |
1da177e4 LT |
288 | mtc0 a0, CP0_STATUS |
289 | li v1, 0xff00 | |
290 | and a0, v1 | |
291 | LONG_L v0, PT_STATUS(sp) | |
292 | nor v1, $0, v1 | |
293 | and v0, v1 | |
294 | or v0, a0 | |
295 | mtc0 v0, CP0_STATUS | |
41c594ab RB |
296 | #ifdef CONFIG_MIPS_MT_SMTC |
297 | /* | |
298 | * Only after EXL/ERL have been restored to status can we | |
299 | * restore TCStatus.IXMT. | |
300 | */ | |
301 | LONG_L v1, PT_TCSTATUS(sp) | |
4277ff5e | 302 | _ehb |
41c594ab RB |
303 | mfc0 v0, CP0_TCSTATUS |
304 | andi v1, TCSTATUS_IXMT | |
305 | /* We know that TCStatua.IXMT should be set from above */ | |
306 | xori v0, v0, TCSTATUS_IXMT | |
307 | or v0, v0, v1 | |
308 | mtc0 v0, CP0_TCSTATUS | |
4277ff5e | 309 | _ehb |
41c594ab RB |
310 | andi a1, a1, VPECONTROL_TE |
311 | beqz a1, 1f | |
312 | emt | |
313 | 1: | |
314 | .set mips0 | |
315 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
316 | LONG_L v1, PT_EPC(sp) |
317 | MTC0 v1, CP0_EPC | |
318 | LONG_L $31, PT_R31(sp) | |
319 | LONG_L $28, PT_R28(sp) | |
320 | LONG_L $25, PT_R25(sp) | |
875d43e7 | 321 | #ifdef CONFIG_64BIT |
1da177e4 LT |
322 | LONG_L $8, PT_R8(sp) |
323 | LONG_L $9, PT_R9(sp) | |
324 | #endif | |
325 | LONG_L $7, PT_R7(sp) | |
326 | LONG_L $6, PT_R6(sp) | |
327 | LONG_L $5, PT_R5(sp) | |
328 | LONG_L $4, PT_R4(sp) | |
329 | LONG_L $3, PT_R3(sp) | |
330 | LONG_L $2, PT_R2(sp) | |
331 | .set pop | |
332 | .endm | |
333 | ||
334 | .macro RESTORE_SP_AND_RET | |
335 | LONG_L sp, PT_R29(sp) | |
336 | .set mips3 | |
337 | eret | |
338 | .set mips0 | |
339 | .endm | |
340 | ||
341 | #endif | |
342 | ||
343 | .macro RESTORE_SP | |
344 | LONG_L sp, PT_R29(sp) | |
345 | .endm | |
346 | ||
347 | .macro RESTORE_ALL | |
348 | RESTORE_TEMP | |
349 | RESTORE_STATIC | |
350 | RESTORE_AT | |
351 | RESTORE_SOME | |
352 | RESTORE_SP | |
353 | .endm | |
354 | ||
355 | .macro RESTORE_ALL_AND_RET | |
356 | RESTORE_TEMP | |
357 | RESTORE_STATIC | |
358 | RESTORE_AT | |
359 | RESTORE_SOME | |
360 | RESTORE_SP_AND_RET | |
361 | .endm | |
362 | ||
363 | /* | |
364 | * Move to kernel mode and disable interrupts. | |
365 | * Set cp0 enable bit as sign that we're running on the kernel stack | |
366 | */ | |
367 | .macro CLI | |
41c594ab | 368 | #if !defined(CONFIG_MIPS_MT_SMTC) |
1da177e4 LT |
369 | mfc0 t0, CP0_STATUS |
370 | li t1, ST0_CU0 | 0x1f | |
371 | or t0, t1 | |
372 | xori t0, 0x1f | |
373 | mtc0 t0, CP0_STATUS | |
41c594ab RB |
374 | #else /* CONFIG_MIPS_MT_SMTC */ |
375 | /* | |
376 | * For SMTC, we need to set privilege | |
377 | * and disable interrupts only for the | |
378 | * current TC, using the TCStatus register. | |
379 | */ | |
380 | mfc0 t0,CP0_TCSTATUS | |
381 | /* Fortunately CU 0 is in the same place in both registers */ | |
382 | /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ | |
383 | li t1, ST0_CU0 | 0x08001c00 | |
384 | or t0,t1 | |
385 | /* Clear TKSU, leave IXMT */ | |
386 | xori t0, 0x00001800 | |
387 | mtc0 t0, CP0_TCSTATUS | |
4277ff5e | 388 | _ehb |
41c594ab RB |
389 | /* We need to leave the global IE bit set, but clear EXL...*/ |
390 | mfc0 t0, CP0_STATUS | |
391 | ori t0, ST0_EXL | ST0_ERL | |
392 | xori t0, ST0_EXL | ST0_ERL | |
393 | mtc0 t0, CP0_STATUS | |
394 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
395 | irq_disable_hazard |
396 | .endm | |
397 | ||
398 | /* | |
399 | * Move to kernel mode and enable interrupts. | |
400 | * Set cp0 enable bit as sign that we're running on the kernel stack | |
401 | */ | |
402 | .macro STI | |
41c594ab | 403 | #if !defined(CONFIG_MIPS_MT_SMTC) |
1da177e4 LT |
404 | mfc0 t0, CP0_STATUS |
405 | li t1, ST0_CU0 | 0x1f | |
406 | or t0, t1 | |
407 | xori t0, 0x1e | |
408 | mtc0 t0, CP0_STATUS | |
41c594ab RB |
409 | #else /* CONFIG_MIPS_MT_SMTC */ |
410 | /* | |
411 | * For SMTC, we need to set privilege | |
412 | * and enable interrupts only for the | |
413 | * current TC, using the TCStatus register. | |
414 | */ | |
4277ff5e | 415 | _ehb |
41c594ab RB |
416 | mfc0 t0,CP0_TCSTATUS |
417 | /* Fortunately CU 0 is in the same place in both registers */ | |
418 | /* Set TCU0, TKSU (for later inversion) and IXMT */ | |
419 | li t1, ST0_CU0 | 0x08001c00 | |
420 | or t0,t1 | |
421 | /* Clear TKSU *and* IXMT */ | |
422 | xori t0, 0x00001c00 | |
423 | mtc0 t0, CP0_TCSTATUS | |
4277ff5e | 424 | _ehb |
41c594ab RB |
425 | /* We need to leave the global IE bit set, but clear EXL...*/ |
426 | mfc0 t0, CP0_STATUS | |
427 | ori t0, ST0_EXL | |
428 | xori t0, ST0_EXL | |
429 | mtc0 t0, CP0_STATUS | |
430 | /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */ | |
431 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
432 | irq_enable_hazard |
433 | .endm | |
434 | ||
435 | /* | |
436 | * Just move to kernel mode and leave interrupts as they are. | |
437 | * Set cp0 enable bit as sign that we're running on the kernel stack | |
438 | */ | |
439 | .macro KMODE | |
41c594ab RB |
440 | #ifdef CONFIG_MIPS_MT_SMTC |
441 | /* | |
442 | * This gets baroque in SMTC. We want to | |
443 | * protect the non-atomic clearing of EXL | |
444 | * with DMT/EMT, but we don't want to take | |
445 | * an interrupt while DMT is still in effect. | |
446 | */ | |
447 | ||
448 | /* KMODE gets invoked from both reorder and noreorder code */ | |
449 | .set push | |
450 | .set mips32r2 | |
451 | .set noreorder | |
452 | mfc0 v0, CP0_TCSTATUS | |
453 | andi v1, v0, TCSTATUS_IXMT | |
454 | ori v0, TCSTATUS_IXMT | |
455 | mtc0 v0, CP0_TCSTATUS | |
4277ff5e | 456 | _ehb |
41c594ab RB |
457 | DMT 2 # dmt v0 |
458 | /* | |
459 | * We don't know a priori if ra is "live" | |
460 | */ | |
461 | move t0, ra | |
462 | jal mips_ihb | |
463 | nop /* delay slot */ | |
464 | move ra, t0 | |
465 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
466 | mfc0 t0, CP0_STATUS |
467 | li t1, ST0_CU0 | 0x1e | |
468 | or t0, t1 | |
469 | xori t0, 0x1e | |
470 | mtc0 t0, CP0_STATUS | |
41c594ab | 471 | #ifdef CONFIG_MIPS_MT_SMTC |
4277ff5e | 472 | _ehb |
41c594ab RB |
473 | andi v0, v0, VPECONTROL_TE |
474 | beqz v0, 2f | |
475 | nop /* delay slot */ | |
476 | emt | |
477 | 2: | |
478 | mfc0 v0, CP0_TCSTATUS | |
479 | /* Clear IXMT, then OR in previous value */ | |
480 | ori v0, TCSTATUS_IXMT | |
481 | xori v0, TCSTATUS_IXMT | |
482 | or v0, v1, v0 | |
483 | mtc0 v0, CP0_TCSTATUS | |
484 | /* | |
485 | * irq_disable_hazard below should expand to EHB | |
486 | * on 24K/34K CPUS | |
487 | */ | |
488 | .set pop | |
489 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
490 | irq_disable_hazard |
491 | .endm | |
492 | ||
493 | #endif /* _ASM_STACKFRAME_H */ |