[deliverable/linux.git] / include / asm-mips / system.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
 * Copyright (C) 1996 by Paul M. Antoine
 * Copyright (C) 1999 Silicon Graphics
 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.
 */
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H

#include <linux/types.h>
#include <linux/irqflags.h>

#include <asm/addrspace.h>
#include <asm/barrier.h>
#include <asm/cpu-features.h>
#include <asm/dsp.h>
#include <asm/war.h>


/*
 * switch_to(n) should switch tasks to task nr n, first
 * checking that n isn't the current task, in which case it does nothing.
 */
extern asmlinkage void *resume(void *last, void *next, void *next_ti);

struct task_struct;

#ifdef CONFIG_MIPS_MT_FPAFF

/*
 * Handle the scheduler resume end of FPU affinity management.  We do this
 * inline to try to keep the overhead down. If we have been forced to run on
 * a "CPU" with an FPU because of a previous high level of FP computation,
 * but did not actually use the FPU during the most recent time-slice (CU1
 * isn't set), we undo the restriction on cpus_allowed.
 *
 * We're not calling set_cpus_allowed() here, because we have no need to
 * force prompt migration - we're already switching the current CPU to a
 * different thread.
 */

#define switch_to(prev,next,last)					\
do {									\
	if (cpu_has_fpu &&						\
	    (prev->thread.mflags & MF_FPUBOUND) &&			\
	     (!(KSTK_STATUS(prev) & ST0_CU1))) {			\
		prev->thread.mflags &= ~MF_FPUBOUND;			\
		prev->cpus_allowed = prev->thread.user_cpus_allowed;	\
	}								\
	if (cpu_has_dsp)						\
		__save_dsp(prev);					\
	next->thread.emulated_fp = 0;					\
	(last) = resume(prev, next, next->thread_info);			\
	if (cpu_has_dsp)						\
		__restore_dsp(current);					\
} while(0)

#else
#define switch_to(prev,next,last)					\
do {									\
	if (cpu_has_dsp)						\
		__save_dsp(prev);					\
	(last) = resume(prev, next, task_thread_info(next));		\
	if (cpu_has_dsp)						\
		__restore_dsp(current);					\
} while(0)
#endif

/*
 * On SMP systems, when the scheduler does migration-cost autodetection,
 * it needs a way to flush as much of the CPU's caches as possible.
 *
 * TODO: fill this in!
 */
static inline void sched_cacheflush(void)
{
}

static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
	__u32 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqz	%2, 2f					\n"
		"	.subsection 2					\n"
		"2:	b	1b					\n"
		"	.previous					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		*m = val;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}

#ifdef CONFIG_64BIT
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
{
	__u64 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqz	%2, 2f					\n"
		"	.subsection 2					\n"
		"2:	b	1b					\n"
		"	.previous					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		*m = val;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}
#else
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
#endif

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid xchg().  */
extern void __xchg_called_with_bad_pointer(void);

static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
	switch (size) {
	case 4:
		return __xchg_u32(ptr, x);
	case 8:
		return __xchg_u64(ptr, x);
	}
	__xchg_called_with_bad_pointer();
	return x;
}

#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
#define tas(ptr) (xchg((ptr),1))

#define __HAVE_ARCH_CMPXCHG 1

static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
	unsigned long new)
{
	__u32 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
		"	bne	%0, %z3, 2f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z4					\n"
		"	.set	mips3					\n"
		"	sc	$1, %1					\n"
		"	beqzl	$1, 1b					\n"
		"2:							\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else if (cpu_has_llsc) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
		"	bne	%0, %z3, 2f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z4					\n"
		"	.set	mips3					\n"
		"	sc	$1, %1					\n"
		"	beqz	$1, 3f					\n"
		"2:							\n"
		"	.subsection 2					\n"
		"3:	b	1b					\n"
		"	.previous					\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		if (retval == old)
			*m = new;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}

#ifdef CONFIG_64BIT
static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
	unsigned long new)
{
	__u64 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
		"	bne	%0, %z3, 2f				\n"
		"	move	$1, %z4					\n"
		"	scd	$1, %1					\n"
		"	beqzl	$1, 1b					\n"
		"2:							\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else if (cpu_has_llsc) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
		"	bne	%0, %z3, 2f				\n"
		"	move	$1, %z4					\n"
		"	scd	$1, %1					\n"
		"	beqz	$1, 3f					\n"
		"2:							\n"
		"	.subsection 2					\n"
		"3:	b	1b					\n"
		"	.previous					\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		if (retval == old)
			*m = new;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}
#else
extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
	volatile int * m, unsigned long old, unsigned long new);
#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
#endif

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid cmpxchg().  */
extern void __cmpxchg_called_with_bad_pointer(void);

static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
	unsigned long new, int size)
{
	switch (size) {
	case 4:
		return __cmpxchg_u32(ptr, old, new);
	case 8:
		return __cmpxchg_u64(ptr, old, new);
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))

extern void set_handler (unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
extern void *set_vi_handler (int n, void *addr);
extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);

extern int stop_a_enabled;

/*
 * See include/asm-ia64/system.h; prevents deadlock on SMP
 * systems.
 */
#define __ARCH_WANT_UNLOCKED_CTXSW

#define arch_align_stack(x) (x)

#endif /* _ASM_SYSTEM_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
0004a9df	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
1da177e4 LT	7	* Copyright (C) 1996 by Paul M. Antoine
	8	* Copyright (C) 1999 Silicon Graphics
	9	* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	*/
	12	#ifndef _ASM_SYSTEM_H
	13	#define _ASM_SYSTEM_H
	14
1da177e4	15	#include <linux/types.h>
192ef366	16	#include <linux/irqflags.h>
1da177e4 LT	17
1da177e4 LT	18	#include <asm/addrspace.h>
0004a9df	19	#include <asm/barrier.h>
1da177e4	20	#include <asm/cpu-features.h>
e50c0a8f	21	#include <asm/dsp.h>
1da177e4	22	#include <asm/war.h>
1da177e4	23
1da177e4	24
1da177e4 LT	25	/*
	26	* switch_to(n) should switch tasks to task nr n, first
	27	* checking that n isn't the current task, in which case it does nothing.
	28	*/
	29	extern asmlinkage void resume(void last, void next, void next_ti);
	30
	31	struct task_struct;
	32
f088fc84 RB	33	#ifdef CONFIG_MIPS_MT_FPAFF
	34
	35	/*
	36	* Handle the scheduler resume end of FPU affinity management. We do this
	37	* inline to try to keep the overhead down. If we have been forced to run on
	38	* a "CPU" with an FPU because of a previous high level of FP computation,
	39	* but did not actually use the FPU during the most recent time-slice (CU1
	40	* isn't set), we undo the restriction on cpus_allowed.
	41	*
	42	* We're not calling set_cpus_allowed() here, because we have no need to
	43	* force prompt migration - we're already switching the current CPU to a
	44	* different thread.
	45	*/
	46
	47	#define switch_to(prev,next,last) \
	48	do { \
	49	if (cpu_has_fpu && \
	50	(prev->thread.mflags & MF_FPUBOUND) && \
	51	(!(KSTK_STATUS(prev) & ST0_CU1))) { \
	52	prev->thread.mflags &= ~MF_FPUBOUND; \
	53	prev->cpus_allowed = prev->thread.user_cpus_allowed; \
	54	} \
	55	if (cpu_has_dsp) \
	56	__save_dsp(prev); \
	57	next->thread.emulated_fp = 0; \
	58	(last) = resume(prev, next, next->thread_info); \
	59	if (cpu_has_dsp) \
	60	__restore_dsp(current); \
	61	} while(0)
	62
	63	#else
e50c0a8f RB	64	#define switch_to(prev,next,last) \
	65	do { \
	66	if (cpu_has_dsp) \
	67	__save_dsp(prev); \
40bc9c67	68	(last) = resume(prev, next, task_thread_info(next)); \
e50c0a8f RB	69	if (cpu_has_dsp) \
e50c0a8f RB	70	__restore_dsp(current); \
1da177e4	71	} while(0)
f088fc84	72	#endif
1da177e4	73
4dc7a0bb IM	74	/*
	75	* On SMP systems, when the scheduler does migration-cost autodetection,
	76	* it needs a way to flush as much of the CPU's caches as possible.
	77	*
	78	* TODO: fill this in!
	79	*/
	80	static inline void sched_cacheflush(void)
	81	{
	82	}
	83
1da177e4 LT	84	static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
	85	{
	86	__u32 retval;
	87
	88	if (cpu_has_llsc && R10000_LLSC_WAR) {
	89	unsigned long dummy;
	90
	91	__asm__ __volatile__(
c4559f67	92	" .set mips3 \n"
1da177e4	93	"1: ll %0, %3 # xchg_u32 \n"
7222424e	94	" .set mips0 \n"
1da177e4	95	" move %2, %z4 \n"
7222424e	96	" .set mips3 \n"
1da177e4 LT	97	" sc %2, %1 \n"
1da177e4 LT	98	" beqzl %2, 1b \n"
aac8aa77	99	" .set mips0 \n"
1da177e4 LT	100	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	101	: "R" (*m), "Jr" (val)
	102	: "memory");
	103	} else if (cpu_has_llsc) {
	104	unsigned long dummy;
	105
	106	__asm__ __volatile__(
c4559f67	107	" .set mips3 \n"
1da177e4	108	"1: ll %0, %3 # xchg_u32 \n"
7222424e	109	" .set mips0 \n"
1da177e4	110	" move %2, %z4 \n"
7222424e	111	" .set mips3 \n"
1da177e4	112	" sc %2, %1 \n"
f65e4fa8 RB	113	" beqz %2, 2f \n"
	114	" .subsection 2 \n"
	115	"2: b 1b \n"
	116	" .previous \n"
aac8aa77	117	" .set mips0 \n"
1da177e4 LT	118	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	119	: "R" (*m), "Jr" (val)
	120	: "memory");
	121	} else {
	122	unsigned long flags;
	123
	124	local_irq_save(flags);
	125	retval = *m;
	126	*m = val;
	127	local_irq_restore(flags); /* implies memory barrier */
	128	}
	129
0004a9df RB	130	smp_mb();
0004a9df RB	131
1da177e4 LT	132	return retval;
	133	}
	134
875d43e7	135	#ifdef CONFIG_64BIT
1da177e4 LT	136	static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
	137	{
	138	__u64 retval;
	139
	140	if (cpu_has_llsc && R10000_LLSC_WAR) {
	141	unsigned long dummy;
	142
	143	__asm__ __volatile__(
aac8aa77	144	" .set mips3 \n"
1da177e4 LT	145	"1: lld %0, %3 # xchg_u64 \n"
	146	" move %2, %z4 \n"
	147	" scd %2, %1 \n"
	148	" beqzl %2, 1b \n"
aac8aa77	149	" .set mips0 \n"
1da177e4 LT	150	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	151	: "R" (*m), "Jr" (val)
	152	: "memory");
	153	} else if (cpu_has_llsc) {
	154	unsigned long dummy;
	155
	156	__asm__ __volatile__(
aac8aa77	157	" .set mips3 \n"
1da177e4 LT	158	"1: lld %0, %3 # xchg_u64 \n"
	159	" move %2, %z4 \n"
	160	" scd %2, %1 \n"
f65e4fa8 RB	161	" beqz %2, 2f \n"
	162	" .subsection 2 \n"
	163	"2: b 1b \n"
	164	" .previous \n"
aac8aa77	165	" .set mips0 \n"
1da177e4 LT	166	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	167	: "R" (*m), "Jr" (val)
	168	: "memory");
	169	} else {
	170	unsigned long flags;
	171
	172	local_irq_save(flags);
	173	retval = *m;
	174	*m = val;
	175	local_irq_restore(flags); /* implies memory barrier */
	176	}
	177
0004a9df RB	178	smp_mb();
0004a9df RB	179
1da177e4 LT	180	return retval;
	181	}
	182	#else
	183	extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
	184	#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
	185	#endif
	186
	187	/* This function doesn't exist, so you'll get a linker error
	188	if something tries to do an invalid xchg(). */
	189	extern void __xchg_called_with_bad_pointer(void);
	190
	191	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
	192	{
	193	switch (size) {
0cea043b RB	194	case 4:
	195	return __xchg_u32(ptr, x);
	196	case 8:
	197	return __xchg_u64(ptr, x);
1da177e4 LT	198	}
	199	__xchg_called_with_bad_pointer();
	200	return x;
	201	}
	202
	203	#define xchg(ptr,x) ((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
	204	#define tas(ptr) (xchg((ptr),1))
	205
	206	#define __HAVE_ARCH_CMPXCHG 1
	207
	208	static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
	209	unsigned long new)
	210	{
	211	__u32 retval;
	212
	213	if (cpu_has_llsc && R10000_LLSC_WAR) {
	214	__asm__ __volatile__(
aac8aa77	215	" .set push \n"
1da177e4	216	" .set noat \n"
c4559f67	217	" .set mips3 \n"
1da177e4 LT	218	"1: ll %0, %2 # __cmpxchg_u32 \n"
1da177e4 LT	219	" bne %0, %z3, 2f \n"
f99d3023	220	" .set mips0 \n"
1da177e4	221	" move $1, %z4 \n"
f99d3023	222	" .set mips3 \n"
1da177e4 LT	223	" sc $1, %1 \n"
1da177e4 LT	224	" beqzl $1, 1b \n"
1da177e4	225	"2: \n"
aac8aa77	226	" .set pop \n"
3e6cb2d3	227	: "=&r" (retval), "=R" (*m)
1da177e4 LT	228	: "R" (*m), "Jr" (old), "Jr" (new)
	229	: "memory");
	230	} else if (cpu_has_llsc) {
	231	__asm__ __volatile__(
aac8aa77	232	" .set push \n"
1da177e4	233	" .set noat \n"
c4559f67	234	" .set mips3 \n"
1da177e4 LT	235	"1: ll %0, %2 # __cmpxchg_u32 \n"
1da177e4 LT	236	" bne %0, %z3, 2f \n"
f99d3023	237	" .set mips0 \n"
1da177e4	238	" move $1, %z4 \n"
f99d3023	239	" .set mips3 \n"
1da177e4	240	" sc $1, %1 \n"
f65e4fa8	241	" beqz $1, 3f \n"
1da177e4	242	"2: \n"
f65e4fa8 RB	243	" .subsection 2 \n"
	244	"3: b 1b \n"
	245	" .previous \n"
aac8aa77	246	" .set pop \n"
3e6cb2d3	247	: "=&r" (retval), "=R" (*m)
1da177e4 LT	248	: "R" (*m), "Jr" (old), "Jr" (new)
	249	: "memory");
	250	} else {
	251	unsigned long flags;
	252
	253	local_irq_save(flags);
	254	retval = *m;
	255	if (retval == old)
	256	*m = new;
	257	local_irq_restore(flags); /* implies memory barrier */
	258	}
	259
0004a9df RB	260	smp_mb();
0004a9df RB	261
1da177e4 LT	262	return retval;
	263	}
	264
875d43e7	265	#ifdef CONFIG_64BIT
1da177e4 LT	266	static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
	267	unsigned long new)
	268	{
	269	__u64 retval;
	270
904880e7	271	if (cpu_has_llsc && R10000_LLSC_WAR) {
1da177e4	272	__asm__ __volatile__(
aac8aa77	273	" .set push \n"
1da177e4	274	" .set noat \n"
aac8aa77	275	" .set mips3 \n"
1da177e4 LT	276	"1: lld %0, %2 # __cmpxchg_u64 \n"
	277	" bne %0, %z3, 2f \n"
	278	" move $1, %z4 \n"
	279	" scd $1, %1 \n"
	280	" beqzl $1, 1b \n"
1da177e4	281	"2: \n"
aac8aa77	282	" .set pop \n"
3e6cb2d3	283	: "=&r" (retval), "=R" (*m)
1da177e4 LT	284	: "R" (*m), "Jr" (old), "Jr" (new)
	285	: "memory");
	286	} else if (cpu_has_llsc) {
	287	__asm__ __volatile__(
aac8aa77	288	" .set push \n"
1da177e4	289	" .set noat \n"
c4559f67	290	" .set mips3 \n"
1da177e4 LT	291	"1: lld %0, %2 # __cmpxchg_u64 \n"
	292	" bne %0, %z3, 2f \n"
	293	" move $1, %z4 \n"
	294	" scd $1, %1 \n"
f65e4fa8	295	" beqz $1, 3f \n"
1da177e4	296	"2: \n"
f65e4fa8 RB	297	" .subsection 2 \n"
	298	"3: b 1b \n"
	299	" .previous \n"
aac8aa77	300	" .set pop \n"
3e6cb2d3	301	: "=&r" (retval), "=R" (*m)
1da177e4 LT	302	: "R" (*m), "Jr" (old), "Jr" (new)
	303	: "memory");
	304	} else {
	305	unsigned long flags;
	306
	307	local_irq_save(flags);
	308	retval = *m;
	309	if (retval == old)
	310	*m = new;
	311	local_irq_restore(flags); /* implies memory barrier */
	312	}
	313
0004a9df RB	314	smp_mb();
0004a9df RB	315
1da177e4 LT	316	return retval;
	317	}
	318	#else
	319	extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
	320	volatile int * m, unsigned long old, unsigned long new);
	321	#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
	322	#endif
	323
	324	/* This function doesn't exist, so you'll get a linker error
	325	if something tries to do an invalid cmpxchg(). */
	326	extern void __cmpxchg_called_with_bad_pointer(void);
	327
	328	static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
	329	unsigned long new, int size)
	330	{
	331	switch (size) {
	332	case 4:
	333	return __cmpxchg_u32(ptr, old, new);
	334	case 8:
	335	return __cmpxchg_u64(ptr, old, new);
	336	}
	337	__cmpxchg_called_with_bad_pointer();
	338	return old;
	339	}
	340
	341	#define cmpxchg(ptr,old,new) ((__typeof__((ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof((ptr))))
	342
e01402b1 RB	343	extern void set_handler (unsigned long offset, void *addr, unsigned long len);
	344	extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
	345	extern void set_vi_handler (int n, void addr);
1da177e4	346	extern void set_except_vector(int n, void addr);
91b05e67	347	extern unsigned long ebase;
1da177e4 LT	348	extern void per_cpu_trap_init(void);
1da177e4 LT	349
1da177e4 LT	350	extern int stop_a_enabled;
	351
	352	/*
4866cde0	353	* See include/asm-ia64/system.h; prevents deadlock on SMP
1da177e4 LT	354	* systems.
1da177e4 LT	355	*/
4866cde0	356	#define __ARCH_WANT_UNLOCKED_CTXSW
1da177e4 LT	357
	358	#define arch_align_stack(x) (x)
	359
	360	#endif /* _ASM_SYSTEM_H */