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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2000-2001 Toshiba Corporation | |
7 | */ | |
42a3b4f2 RB |
8 | #ifndef __ASM_TX4927_TX4927_PCI_H |
9 | #define __ASM_TX4927_TX4927_PCI_H | |
1da177e4 LT |
10 | |
11 | #define TX4927_CCFG_TOE 0x00004000 | |
229f773e | 12 | #define TX4927_CCFG_TINTDIS 0x01000000 |
1da177e4 LT |
13 | |
14 | #define TX4927_PCIMEM 0x08000000 | |
15 | #define TX4927_PCIMEM_SIZE 0x08000000 | |
16 | #define TX4927_PCIIO 0x16000000 | |
17 | #define TX4927_PCIIO_SIZE 0x01000000 | |
18 | ||
19 | #define TX4927_SDRAMC_REG 0xff1f8000 | |
20 | #define TX4927_EBUSC_REG 0xff1f9000 | |
21 | #define TX4927_PCIC_REG 0xff1fd000 | |
22 | #define TX4927_CCFG_REG 0xff1fe000 | |
23 | #define TX4927_IRC_REG 0xff1ff600 | |
229f773e AN |
24 | #define TX4927_NR_TMR 3 |
25 | #define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) | |
1da177e4 LT |
26 | #define TX4927_CE3 0x17f00000 /* 1M */ |
27 | #define TX4927_PCIRESET_ADDR 0xbc00f006 | |
28 | #define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) | |
29 | ||
30 | #define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n)) | |
31 | #define tx4927_imstat_ptr(n) \ | |
32 | ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n)) | |
33 | ||
34 | /* bits for ISTAT3/IMASK3/IMSTAT3 */ | |
35 | #define TX4927_INT3B_PCID 0 | |
36 | #define TX4927_INT3B_PCIC 1 | |
37 | #define TX4927_INT3B_PCIB 2 | |
38 | #define TX4927_INT3B_PCIA 3 | |
39 | #define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) | |
40 | #define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) | |
41 | #define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) | |
42 | #define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) | |
43 | ||
44 | /* bits for PCI_CLK (S6) */ | |
45 | #define TX4927_PCI_CLK_HOST 0x80 | |
46 | #define TX4927_PCI_CLK_MASK (0x0f << 3) | |
47 | #define TX4927_PCI_CLK_33 (0x01 << 3) | |
48 | #define TX4927_PCI_CLK_25 (0x04 << 3) | |
49 | #define TX4927_PCI_CLK_66 (0x09 << 3) | |
50 | #define TX4927_PCI_CLK_50 (0x0c << 3) | |
51 | #define TX4927_PCI_CLK_ACK 0x04 | |
52 | #define TX4927_PCI_CLK_ACE 0x02 | |
53 | #define TX4927_PCI_CLK_ENDIAN 0x01 | |
c87abd75 | 54 | #define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG |
1da177e4 LT |
55 | #define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ |
56 | ||
57 | #define TX4927_IR_PCIC 16 | |
58 | #define TX4927_IR_PCIERR 22 | |
59 | #define TX4927_IR_PCIPMA 23 | |
60 | #define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) | |
61 | #define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) | |
62 | #define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) | |
63 | #define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) | |
64 | #define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) | |
65 | #define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) | |
66 | #define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) | |
67 | ||
68 | #ifdef _LANGUAGE_ASSEMBLY | |
69 | #define _CONST64(c) c | |
70 | #else | |
71 | #define _CONST64(c) c##ull | |
72 | ||
73 | #include <asm/byteorder.h> | |
74 | ||
75 | #define tx4927_pcireset_ptr \ | |
76 | ((volatile unsigned char *)TX4927_PCIRESET_ADDR) | |
77 | #define tx4927_pci_clk_ptr \ | |
78 | ((volatile unsigned char *)TX4927_PCI_CLK_ADDR) | |
79 | ||
80 | struct tx4927_sdramc_reg { | |
81 | volatile unsigned long long cr[4]; | |
82 | volatile unsigned long long unused0[4]; | |
83 | volatile unsigned long long tr; | |
84 | volatile unsigned long long unused1[2]; | |
85 | volatile unsigned long long cmd; | |
86 | }; | |
87 | ||
88 | struct tx4927_ebusc_reg { | |
89 | volatile unsigned long long cr[8]; | |
90 | }; | |
91 | ||
92 | struct tx4927_ccfg_reg { | |
93 | volatile unsigned long long ccfg; | |
94 | volatile unsigned long long crir; | |
95 | volatile unsigned long long pcfg; | |
96 | volatile unsigned long long tear; | |
97 | volatile unsigned long long clkctr; | |
98 | volatile unsigned long long unused0; | |
99 | volatile unsigned long long garbc; | |
100 | volatile unsigned long long unused1; | |
101 | volatile unsigned long long unused2; | |
102 | volatile unsigned long long ramp; | |
103 | }; | |
104 | ||
1da177e4 LT |
105 | struct tx4927_pcic_reg { |
106 | volatile unsigned long pciid; | |
107 | volatile unsigned long pcistatus; | |
108 | volatile unsigned long pciccrev; | |
109 | volatile unsigned long pcicfg1; | |
110 | volatile unsigned long p2gm0plbase; /* +10 */ | |
111 | volatile unsigned long p2gm0pubase; | |
112 | volatile unsigned long p2gm1plbase; | |
113 | volatile unsigned long p2gm1pubase; | |
114 | volatile unsigned long p2gm2pbase; /* +20 */ | |
115 | volatile unsigned long p2giopbase; | |
116 | volatile unsigned long unused0; | |
117 | volatile unsigned long pcisid; | |
118 | volatile unsigned long unused1; /* +30 */ | |
119 | volatile unsigned long pcicapptr; | |
120 | volatile unsigned long unused2; | |
121 | volatile unsigned long pcicfg2; | |
122 | volatile unsigned long g2ptocnt; /* +40 */ | |
123 | volatile unsigned long unused3[15]; | |
124 | volatile unsigned long g2pstatus; /* +80 */ | |
125 | volatile unsigned long g2pmask; | |
126 | volatile unsigned long pcisstatus; | |
127 | volatile unsigned long pcimask; | |
128 | volatile unsigned long p2gcfg; /* +90 */ | |
129 | volatile unsigned long p2gstatus; | |
130 | volatile unsigned long p2gmask; | |
131 | volatile unsigned long p2gccmd; | |
132 | volatile unsigned long unused4[24]; /* +a0 */ | |
133 | volatile unsigned long pbareqport; /* +100 */ | |
134 | volatile unsigned long pbacfg; | |
135 | volatile unsigned long pbastatus; | |
136 | volatile unsigned long pbamask; | |
137 | volatile unsigned long pbabm; /* +110 */ | |
138 | volatile unsigned long pbacreq; | |
139 | volatile unsigned long pbacgnt; | |
140 | volatile unsigned long pbacstate; | |
141 | volatile unsigned long long g2pmgbase[3]; /* +120 */ | |
142 | volatile unsigned long long g2piogbase; | |
143 | volatile unsigned long g2pmmask[3]; /* +140 */ | |
144 | volatile unsigned long g2piomask; | |
145 | volatile unsigned long long g2pmpbase[3]; /* +150 */ | |
146 | volatile unsigned long long g2piopbase; | |
147 | volatile unsigned long pciccfg; /* +170 */ | |
148 | volatile unsigned long pcicstatus; | |
149 | volatile unsigned long pcicmask; | |
150 | volatile unsigned long unused5; | |
151 | volatile unsigned long long p2gmgbase[3]; /* +180 */ | |
152 | volatile unsigned long long p2giogbase; | |
153 | volatile unsigned long g2pcfgadrs; /* +1a0 */ | |
154 | volatile unsigned long g2pcfgdata; | |
155 | volatile unsigned long unused6[8]; | |
156 | volatile unsigned long g2pintack; | |
157 | volatile unsigned long g2pspc; | |
158 | volatile unsigned long unused7[12]; /* +1d0 */ | |
159 | volatile unsigned long long pdmca; /* +200 */ | |
160 | volatile unsigned long long pdmga; | |
161 | volatile unsigned long long pdmpa; | |
162 | volatile unsigned long long pdmcut; | |
163 | volatile unsigned long long pdmcnt; /* +220 */ | |
164 | volatile unsigned long long pdmsts; | |
165 | volatile unsigned long long unused8[2]; | |
166 | volatile unsigned long long pdmdb[4]; /* +240 */ | |
167 | volatile unsigned long long pdmtdh; /* +260 */ | |
168 | volatile unsigned long long pdmdms; | |
169 | }; | |
170 | ||
171 | #endif /* _LANGUAGE_ASSEMBLY */ | |
172 | ||
1da177e4 LT |
173 | /* |
174 | * PCIC | |
175 | */ | |
176 | ||
177 | /* bits for G2PSTATUS/G2PMASK */ | |
178 | #define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 | |
179 | #define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 | |
180 | #define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 | |
181 | ||
182 | /* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ | |
183 | #define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 | |
184 | ||
185 | /* bits for PBACFG */ | |
186 | #define TX4927_PCIC_PBACFG_RPBA 0x00000004 | |
187 | #define TX4927_PCIC_PBACFG_PBAEN 0x00000002 | |
188 | #define TX4927_PCIC_PBACFG_BMCEN 0x00000001 | |
189 | ||
190 | /* bits for G2PMnGBASE */ | |
191 | #define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) | |
192 | #define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) | |
193 | ||
194 | /* bits for G2PIOGBASE */ | |
195 | #define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) | |
196 | #define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) | |
197 | ||
198 | /* bits for PCICSTATUS/PCICMASK */ | |
199 | #define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc | |
200 | ||
201 | /* bits for PCICCFG */ | |
202 | #define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 | |
203 | #define TX4927_PCIC_PCICCFG_HRST 0x00000800 | |
204 | #define TX4927_PCIC_PCICCFG_SRST 0x00000400 | |
205 | #define TX4927_PCIC_PCICCFG_IRBER 0x00000200 | |
206 | #define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 | |
207 | #define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 | |
208 | #define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 | |
209 | #define TX4927_PCIC_PCICCFG_IISE 0x00000020 | |
210 | #define TX4927_PCIC_PCICCFG_ATR 0x00000010 | |
211 | #define TX4927_PCIC_PCICCFG_ICAE 0x00000008 | |
212 | ||
213 | /* bits for P2GMnGBASE */ | |
214 | #define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) | |
215 | #define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) | |
216 | #define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) | |
217 | ||
218 | /* bits for P2GIOGBASE */ | |
219 | #define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) | |
220 | #define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) | |
221 | #define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) | |
222 | ||
223 | #define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) | |
224 | #define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) | |
225 | ||
226 | /* | |
227 | * CCFG | |
228 | */ | |
229 | /* CCFG : Chip Configuration */ | |
230 | #define TX4927_CCFG_PCI66 0x00800000 | |
231 | #define TX4927_CCFG_PCIMIDE 0x00400000 | |
232 | #define TX4927_CCFG_PCIXARB 0x00002000 | |
233 | #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 | |
234 | #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 | |
235 | #define TX4927_CCFG_PCIDIVMODE_3 0x00000800 | |
236 | #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 | |
237 | #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 | |
238 | ||
f09678af SS |
239 | #define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 |
240 | #define TX4937_CCFG_PCIDIVMODE_8 0x00000000 | |
241 | #define TX4937_CCFG_PCIDIVMODE_4 0x00000400 | |
242 | #define TX4937_CCFG_PCIDIVMODE_9 0x00000800 | |
243 | #define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 | |
244 | #define TX4937_CCFG_PCIDIVMODE_10 0x00001000 | |
245 | #define TX4937_CCFG_PCIDIVMODE_5 0x00001400 | |
246 | #define TX4937_CCFG_PCIDIVMODE_11 0x00001800 | |
247 | #define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 | |
248 | ||
1da177e4 LT |
249 | /* PCFG : Pin Configuration */ |
250 | #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 | |
251 | #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) | |
252 | ||
253 | /* CLKCTR : Clock Control */ | |
254 | #define TX4927_CLKCTR_PCICKD 0x00400000 | |
255 | #define TX4927_CLKCTR_PCIRST 0x00000040 | |
256 | ||
257 | ||
258 | #ifndef _LANGUAGE_ASSEMBLY | |
259 | ||
260 | #define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) | |
261 | #define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) | |
262 | #define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) | |
263 | #define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) | |
1da177e4 LT |
264 | |
265 | #endif /* _LANGUAGE_ASSEMBLY */ | |
266 | ||
267 | #endif /* __ASM_TX4927_TX4927_PCI_H */ |