[deliverable/linux.git] / include / asm-parisc / assembly.h

/*
 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
 * Copyright (C) 1999 SuSE GmbH
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _PARISC_ASSEMBLY_H
#define _PARISC_ASSEMBLY_H

#define CALLEE_FLOAT_FRAME_SIZE	80

#ifdef CONFIG_64BIT
#define LDREG	ldd
#define STREG	std
#define LDREGX  ldd,s
#define LDREGM	ldd,mb
#define STREGM	std,ma
#define SHRREG	shrd
#define SHLREG	shld
#define RP_OFFSET	16
#define FRAME_SIZE	128
#define CALLEE_REG_FRAME_SIZE	144
#else	/* CONFIG_64BIT */
#define LDREG	ldw
#define STREG	stw
#define LDREGX  ldwx,s
#define LDREGM	ldwm
#define STREGM	stwm
#define SHRREG	shr
#define SHLREG	shlw
#define RP_OFFSET	20
#define FRAME_SIZE	64
#define CALLEE_REG_FRAME_SIZE	128
#endif

#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)

#ifdef CONFIG_PA20
#define LDCW		ldcw,co
#define BL		b,l
# ifdef CONFIG_64BIT
#  define LEVEL		2.0w
# else
#  define LEVEL		2.0
# endif
#else
#define LDCW		ldcw
#define BL		bl
#define LEVEL		1.1
#endif

#ifdef __ASSEMBLY__

#ifdef __LP64__
/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
 * work around that for now... */
	.level 2.0w
#endif

#include <asm/asm-offsets.h>
#include <asm/page.h>

#include <asm/asmregs.h>

	sp	=	30
	gp	=	27
	ipsw	=	22

	/*
	 * We provide two versions of each macro to convert from physical
	 * to virtual and vice versa. The "_r1" versions take one argument
	 * register, but trashes r1 to do the conversion. The other
	 * version takes two arguments: a src and destination register.
	 * However, the source and destination registers can not be
	 * the same register.
	 */

	.macro  tophys  grvirt, grphys
	ldil    L%(__PAGE_OFFSET), \grphys
	sub     \grvirt, \grphys, \grphys
	.endm
	
	.macro  tovirt  grphys, grvirt
	ldil    L%(__PAGE_OFFSET), \grvirt
	add     \grphys, \grvirt, \grvirt
	.endm

	.macro  tophys_r1  gr
	ldil    L%(__PAGE_OFFSET), %r1
	sub     \gr, %r1, \gr
	.endm
	
	.macro  tovirt_r1  gr
	ldil    L%(__PAGE_OFFSET), %r1
	add     \gr, %r1, \gr
	.endm

	.macro delay value
	ldil	L%\value, 1
	ldo	R%\value(1), 1
	addib,UV,n -1,1,.
	addib,NUV,n -1,1,.+8
	nop
	.endm

	.macro	debug value
	.endm


	/* Shift Left - note the r and t can NOT be the same! */
	.macro shl r, sa, t
	dep,z	\r, 31-\sa, 32-\sa, \t
	.endm

	/* The PA 2.0 shift left */
	.macro shlw r, sa, t
	depw,z	\r, 31-\sa, 32-\sa, \t
	.endm

	/* And the PA 2.0W shift left */
	.macro shld r, sa, t
	depd,z	\r, 63-\sa, 64-\sa, \t
	.endm

	/* Shift Right - note the r and t can NOT be the same! */
	.macro shr r, sa, t
	extru \r, 31-\sa, 32-\sa, \t
	.endm

	/* pa20w version of shift right */
	.macro shrd r, sa, t
	extrd,u \r, 63-\sa, 64-\sa, \t
	.endm

	/* load 32-bit 'value' into 'reg' compensating for the ldil
	 * sign-extension when running in wide mode.
	 * WARNING!! neither 'value' nor 'reg' can be expressions
	 * containing '.'!!!! */
	.macro	load32 value, reg
	ldil	L%\value, \reg
	ldo	R%\value(\reg), \reg
	.endm

	.macro loadgp
#ifdef __LP64__
	ldil		L%__gp, %r27
	ldo		R%__gp(%r27), %r27
#else
	ldil		L%$global$, %r27
	ldo		R%$global$(%r27), %r27
#endif
	.endm

#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r

	.macro	save_general	regs
	STREG %r1, PT_GR1 (\regs)
	STREG %r2, PT_GR2 (\regs)
	STREG %r3, PT_GR3 (\regs)
	STREG %r4, PT_GR4 (\regs)
	STREG %r5, PT_GR5 (\regs)
	STREG %r6, PT_GR6 (\regs)
	STREG %r7, PT_GR7 (\regs)
	STREG %r8, PT_GR8 (\regs)
	STREG %r9, PT_GR9 (\regs)
	STREG %r10, PT_GR10(\regs)
	STREG %r11, PT_GR11(\regs)
	STREG %r12, PT_GR12(\regs)
	STREG %r13, PT_GR13(\regs)
	STREG %r14, PT_GR14(\regs)
	STREG %r15, PT_GR15(\regs)
	STREG %r16, PT_GR16(\regs)
	STREG %r17, PT_GR17(\regs)
	STREG %r18, PT_GR18(\regs)
	STREG %r19, PT_GR19(\regs)
	STREG %r20, PT_GR20(\regs)
	STREG %r21, PT_GR21(\regs)
	STREG %r22, PT_GR22(\regs)
	STREG %r23, PT_GR23(\regs)
	STREG %r24, PT_GR24(\regs)
	STREG %r25, PT_GR25(\regs)
	/* r26 is saved in get_stack and used to preserve a value across virt_map */
	STREG %r27, PT_GR27(\regs)
	STREG %r28, PT_GR28(\regs)
	/* r29 is saved in get_stack and used to point to saved registers */
	/* r30 stack pointer saved in get_stack */
	STREG %r31, PT_GR31(\regs)
	.endm

	.macro	rest_general	regs
	/* r1 used as a temp in rest_stack and is restored there */
	LDREG PT_GR2 (\regs), %r2
	LDREG PT_GR3 (\regs), %r3
	LDREG PT_GR4 (\regs), %r4
	LDREG PT_GR5 (\regs), %r5
	LDREG PT_GR6 (\regs), %r6
	LDREG PT_GR7 (\regs), %r7
	LDREG PT_GR8 (\regs), %r8
	LDREG PT_GR9 (\regs), %r9
	LDREG PT_GR10(\regs), %r10
	LDREG PT_GR11(\regs), %r11
	LDREG PT_GR12(\regs), %r12
	LDREG PT_GR13(\regs), %r13
	LDREG PT_GR14(\regs), %r14
	LDREG PT_GR15(\regs), %r15
	LDREG PT_GR16(\regs), %r16
	LDREG PT_GR17(\regs), %r17
	LDREG PT_GR18(\regs), %r18
	LDREG PT_GR19(\regs), %r19
	LDREG PT_GR20(\regs), %r20
	LDREG PT_GR21(\regs), %r21
	LDREG PT_GR22(\regs), %r22
	LDREG PT_GR23(\regs), %r23
	LDREG PT_GR24(\regs), %r24
	LDREG PT_GR25(\regs), %r25
	LDREG PT_GR26(\regs), %r26
	LDREG PT_GR27(\regs), %r27
	LDREG PT_GR28(\regs), %r28
	/* r29 points to register save area, and is restored in rest_stack */
	/* r30 stack pointer restored in rest_stack */
	LDREG PT_GR31(\regs), %r31
	.endm

	.macro	save_fp 	regs
	fstd,ma  %fr0, 8(\regs)
	fstd,ma	 %fr1, 8(\regs)
	fstd,ma	 %fr2, 8(\regs)
	fstd,ma	 %fr3, 8(\regs)
	fstd,ma	 %fr4, 8(\regs)
	fstd,ma	 %fr5, 8(\regs)
	fstd,ma	 %fr6, 8(\regs)
	fstd,ma	 %fr7, 8(\regs)
	fstd,ma	 %fr8, 8(\regs)
	fstd,ma	 %fr9, 8(\regs)
	fstd,ma	%fr10, 8(\regs)
	fstd,ma	%fr11, 8(\regs)
	fstd,ma	%fr12, 8(\regs)
	fstd,ma	%fr13, 8(\regs)
	fstd,ma	%fr14, 8(\regs)
	fstd,ma	%fr15, 8(\regs)
	fstd,ma	%fr16, 8(\regs)
	fstd,ma	%fr17, 8(\regs)
	fstd,ma	%fr18, 8(\regs)
	fstd,ma	%fr19, 8(\regs)
	fstd,ma	%fr20, 8(\regs)
	fstd,ma	%fr21, 8(\regs)
	fstd,ma	%fr22, 8(\regs)
	fstd,ma	%fr23, 8(\regs)
	fstd,ma	%fr24, 8(\regs)
	fstd,ma	%fr25, 8(\regs)
	fstd,ma	%fr26, 8(\regs)
	fstd,ma	%fr27, 8(\regs)
	fstd,ma	%fr28, 8(\regs)
	fstd,ma	%fr29, 8(\regs)
	fstd,ma	%fr30, 8(\regs)
	fstd	%fr31, 0(\regs)
	.endm

	.macro	rest_fp 	regs
	fldd	0(\regs),	 %fr31
	fldd,mb	-8(\regs),       %fr30
	fldd,mb	-8(\regs),       %fr29
	fldd,mb	-8(\regs),       %fr28
	fldd,mb	-8(\regs),       %fr27
	fldd,mb	-8(\regs),       %fr26
	fldd,mb	-8(\regs),       %fr25
	fldd,mb	-8(\regs),       %fr24
	fldd,mb	-8(\regs),       %fr23
	fldd,mb	-8(\regs),       %fr22
	fldd,mb	-8(\regs),       %fr21
	fldd,mb	-8(\regs),       %fr20
	fldd,mb	-8(\regs),       %fr19
	fldd,mb	-8(\regs),       %fr18
	fldd,mb	-8(\regs),       %fr17
	fldd,mb	-8(\regs),       %fr16
	fldd,mb	-8(\regs),       %fr15
	fldd,mb	-8(\regs),       %fr14
	fldd,mb	-8(\regs),       %fr13
	fldd,mb	-8(\regs),       %fr12
	fldd,mb	-8(\regs),       %fr11
	fldd,mb	-8(\regs),       %fr10
	fldd,mb	-8(\regs),       %fr9
	fldd,mb	-8(\regs),       %fr8
	fldd,mb	-8(\regs),       %fr7
	fldd,mb	-8(\regs),       %fr6
	fldd,mb	-8(\regs),       %fr5
	fldd,mb	-8(\regs),       %fr4
	fldd,mb	-8(\regs),       %fr3
	fldd,mb	-8(\regs),       %fr2
	fldd,mb	-8(\regs),       %fr1
	fldd,mb	-8(\regs),       %fr0
	.endm

	.macro	callee_save_float
	fstd,ma	 %fr12,	8(%r30)
	fstd,ma	 %fr13,	8(%r30)
	fstd,ma	 %fr14,	8(%r30)
	fstd,ma	 %fr15,	8(%r30)
	fstd,ma	 %fr16,	8(%r30)
	fstd,ma	 %fr17,	8(%r30)
	fstd,ma	 %fr18,	8(%r30)
	fstd,ma	 %fr19,	8(%r30)
	fstd,ma	 %fr20,	8(%r30)
	fstd,ma	 %fr21,	8(%r30)
	.endm

	.macro	callee_rest_float
	fldd,mb	-8(%r30),   %fr21
	fldd,mb	-8(%r30),   %fr20
	fldd,mb	-8(%r30),   %fr19
	fldd,mb	-8(%r30),   %fr18
	fldd,mb	-8(%r30),   %fr17
	fldd,mb	-8(%r30),   %fr16
	fldd,mb	-8(%r30),   %fr15
	fldd,mb	-8(%r30),   %fr14
	fldd,mb	-8(%r30),   %fr13
	fldd,mb	-8(%r30),   %fr12
	.endm

#ifdef __LP64__
	.macro	callee_save
	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)
	mfctl	  %cr27, %r3
	std	  %r4,	-136(%r30)
	std	  %r5,	-128(%r30)
	std	  %r6,	-120(%r30)
	std	  %r7,	-112(%r30)
	std	  %r8,	-104(%r30)
	std	  %r9,	 -96(%r30)
	std	 %r10,	 -88(%r30)
	std	 %r11,	 -80(%r30)
	std	 %r12,	 -72(%r30)
	std	 %r13,	 -64(%r30)
	std	 %r14,	 -56(%r30)
	std	 %r15,	 -48(%r30)
	std	 %r16,	 -40(%r30)
	std	 %r17,	 -32(%r30)
	std	 %r18,	 -24(%r30)
	std	  %r3,	 -16(%r30)
	.endm

	.macro	callee_rest
	ldd	 -16(%r30),    %r3
	ldd	 -24(%r30),   %r18
	ldd	 -32(%r30),   %r17
	ldd	 -40(%r30),   %r16
	ldd	 -48(%r30),   %r15
	ldd	 -56(%r30),   %r14
	ldd	 -64(%r30),   %r13
	ldd	 -72(%r30),   %r12
	ldd	 -80(%r30),   %r11
	ldd	 -88(%r30),   %r10
	ldd	 -96(%r30),    %r9
	ldd	-104(%r30),    %r8
	ldd	-112(%r30),    %r7
	ldd	-120(%r30),    %r6
	ldd	-128(%r30),    %r5
	ldd	-136(%r30),    %r4
	mtctl	%r3, %cr27
	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3
	.endm

#else /* ! __LP64__ */

	.macro	callee_save
	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
	mfctl	 %cr27, %r3
	stw	 %r4,	-124(%r30)
	stw	 %r5,	-120(%r30)
	stw	 %r6,	-116(%r30)
	stw	 %r7,	-112(%r30)
	stw	 %r8,	-108(%r30)
	stw	 %r9,	-104(%r30)
	stw	 %r10,	-100(%r30)
	stw	 %r11,	 -96(%r30)
	stw	 %r12,	 -92(%r30)
	stw	 %r13,	 -88(%r30)
	stw	 %r14,	 -84(%r30)
	stw	 %r15,	 -80(%r30)
	stw	 %r16,	 -76(%r30)
	stw	 %r17,	 -72(%r30)
	stw	 %r18,	 -68(%r30)
	stw	  %r3,	 -64(%r30)
	.endm

	.macro	callee_rest
	ldw	 -64(%r30),    %r3
	ldw	 -68(%r30),   %r18
	ldw	 -72(%r30),   %r17
	ldw	 -76(%r30),   %r16
	ldw	 -80(%r30),   %r15
	ldw	 -84(%r30),   %r14
	ldw	 -88(%r30),   %r13
	ldw	 -92(%r30),   %r12
	ldw	 -96(%r30),   %r11
	ldw	-100(%r30),   %r10
	ldw	-104(%r30),   %r9
	ldw	-108(%r30),   %r8
	ldw	-112(%r30),   %r7
	ldw	-116(%r30),   %r6
	ldw	-120(%r30),   %r5
	ldw	-124(%r30),   %r4
	mtctl	%r3, %cr27
	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3
	.endm
#endif /* ! __LP64__ */

	.macro	save_specials	regs

	SAVE_SP  (%sr0, PT_SR0 (\regs))
	SAVE_SP  (%sr1, PT_SR1 (\regs))
	SAVE_SP  (%sr2, PT_SR2 (\regs))
	SAVE_SP  (%sr3, PT_SR3 (\regs))
	SAVE_SP  (%sr4, PT_SR4 (\regs))
	SAVE_SP  (%sr5, PT_SR5 (\regs))
	SAVE_SP  (%sr6, PT_SR6 (\regs))
	SAVE_SP  (%sr7, PT_SR7 (\regs))

	SAVE_CR  (%cr17, PT_IASQ0(\regs))
	mtctl	 %r0,	%cr17
	SAVE_CR  (%cr17, PT_IASQ1(\regs))

	SAVE_CR  (%cr18, PT_IAOQ0(\regs))
	mtctl	 %r0,	%cr18
	SAVE_CR  (%cr18, PT_IAOQ1(\regs))

#ifdef __LP64__
	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
	 * we lose the 6th bit on a save/restore over interrupt.
	 */
	mfctl,w  %cr11, %r1
	STREG    %r1, PT_SAR (\regs)
#else
	SAVE_CR  (%cr11, PT_SAR  (\regs))
#endif
	SAVE_CR  (%cr19, PT_IIR  (\regs))

	/*
	 * Code immediately following this macro (in intr_save) relies
	 * on r8 containing ipsw.
	 */
	mfctl    %cr22, %r8
	STREG    %r8,   PT_PSW(\regs)
	.endm

	.macro	rest_specials	regs

	REST_SP  (%sr0, PT_SR0 (\regs))
	REST_SP  (%sr1, PT_SR1 (\regs))
	REST_SP  (%sr2, PT_SR2 (\regs))
	REST_SP  (%sr3, PT_SR3 (\regs))
	REST_SP  (%sr4, PT_SR4 (\regs))
	REST_SP  (%sr5, PT_SR5 (\regs))
	REST_SP  (%sr6, PT_SR6 (\regs))
	REST_SP  (%sr7, PT_SR7 (\regs))

	REST_CR	(%cr17, PT_IASQ0(\regs))
	REST_CR	(%cr17, PT_IASQ1(\regs))

	REST_CR	(%cr18, PT_IAOQ0(\regs))
	REST_CR	(%cr18, PT_IAOQ1(\regs))

	REST_CR (%cr11, PT_SAR	(\regs))

	REST_CR	(%cr22, PT_PSW	(\regs))
	.endm


	/* First step to create a "relied upon translation"
	 * See PA 2.0 Arch. page F-4 and F-5.
	 *
	 * The ssm was originally necessary due to a "PCxT bug".
	 * But someone decided it needed to be added to the architecture
	 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
	 * It's been carried forward into PA 2.0 Arch as well. :^(
	 *
	 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
	 * rsm/ssm prevents the ifetch unit from speculatively fetching
	 * instructions past this line in the code stream.
	 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
	 */
	.macro	pcxt_ssm_bug
	rsm	PSW_SM_I,%r0
	nop	/* 1 */
	nop	/* 2 */
	nop	/* 3 */
	nop	/* 4 */
	nop	/* 5 */
	nop	/* 6 */
	nop	/* 7 */
	.endm

#endif /* __ASSEMBLY__ */
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
	3	* Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
	4	* Copyright (C) 1999 SuSE GmbH
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2, or (at your option)
	9	* any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#ifndef _PARISC_ASSEMBLY_H
	22	#define _PARISC_ASSEMBLY_H
	23
618febd6	24	#define CALLEE_FLOAT_FRAME_SIZE 80
61520e1f GG	25
61520e1f GG	26	#ifdef CONFIG_64BIT
1da177e4 LT	27	#define LDREG ldd
	28	#define STREG std
	29	#define LDREGX ldd,s
	30	#define LDREGM ldd,mb
	31	#define STREGM std,ma
3d73cf5e KM	32	#define SHRREG shrd
3d73cf5e KM	33	#define SHLREG shld
1da177e4 LT	34	#define RP_OFFSET 16
1da177e4 LT	35	#define FRAME_SIZE 128
618febd6	36	#define CALLEE_REG_FRAME_SIZE 144
61520e1f	37	#else /* CONFIG_64BIT */
1da177e4 LT	38	#define LDREG ldw
	39	#define STREG stw
	40	#define LDREGX ldwx,s
	41	#define LDREGM ldwm
	42	#define STREGM stwm
3d73cf5e KM	43	#define SHRREG shr
3d73cf5e KM	44	#define SHLREG shlw
1da177e4 LT	45	#define RP_OFFSET 20
1da177e4 LT	46	#define FRAME_SIZE 64
618febd6	47	#define CALLEE_REG_FRAME_SIZE 128
1da177e4	48	#endif
61520e1f	49
618febd6	50	#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
1da177e4 LT	51
1da177e4 LT	52	#ifdef CONFIG_PA20
64f49532	53	#define LDCW ldcw,co
1da177e4 LT	54	#define BL b,l
	55	# ifdef CONFIG_64BIT
	56	# define LEVEL 2.0w
	57	# else
	58	# define LEVEL 2.0
	59	# endif
	60	#else
64f49532	61	#define LDCW ldcw
1da177e4 LT	62	#define BL bl
	63	#define LEVEL 1.1
	64	#endif
	65
	66	#ifdef __ASSEMBLY__
	67
	68	#ifdef __LP64__
	69	/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
	70	* work around that for now... */
	71	.level 2.0w
	72	#endif
	73
0013a854	74	#include <asm/asm-offsets.h>
1da177e4 LT	75	#include <asm/page.h>
	76
	77	#include <asm/asmregs.h>
	78
	79	sp = 30
	80	gp = 27
	81	ipsw = 22
	82
	83	/*
	84	* We provide two versions of each macro to convert from physical
	85	* to virtual and vice versa. The "_r1" versions take one argument
	86	* register, but trashes r1 to do the conversion. The other
	87	* version takes two arguments: a src and destination register.
	88	* However, the source and destination registers can not be
	89	* the same register.
	90	*/
	91
	92	.macro tophys grvirt, grphys
	93	ldil L%(__PAGE_OFFSET), \grphys
	94	sub \grvirt, \grphys, \grphys
	95	.endm
	96
	97	.macro tovirt grphys, grvirt
	98	ldil L%(__PAGE_OFFSET), \grvirt
	99	add \grphys, \grvirt, \grvirt
	100	.endm
	101
	102	.macro tophys_r1 gr
	103	ldil L%(__PAGE_OFFSET), %r1
	104	sub \gr, %r1, \gr
	105	.endm
	106
	107	.macro tovirt_r1 gr
	108	ldil L%(__PAGE_OFFSET), %r1
	109	add \gr, %r1, \gr
	110	.endm
	111
	112	.macro delay value
	113	ldil L%\value, 1
	114	ldo R%\value(1), 1
	115	addib,UV,n -1,1,.
	116	addib,NUV,n -1,1,.+8
	117	nop
	118	.endm
	119
	120	.macro debug value
	121	.endm
	122
	123
	124	/* Shift Left - note the r and t can NOT be the same! */
	125	.macro shl r, sa, t
	126	dep,z \r, 31-\sa, 32-\sa, \t
	127	.endm
	128
	129	/* The PA 2.0 shift left */
	130	.macro shlw r, sa, t
	131	depw,z \r, 31-\sa, 32-\sa, \t
	132	.endm
	133
	134	/* And the PA 2.0W shift left */
	135	.macro shld r, sa, t
	136	depd,z \r, 63-\sa, 64-\sa, \t
	137	.endm
	138
139	/* Shift Right - note the r and t can NOT be the same! */
140	.macro shr r, sa, t
141	extru \r, 31-\sa, 32-\sa, \t
142	.endm
143
144	/* pa20w version of shift right */
145	.macro shrd r, sa, t
146	extrd,u \r, 63-\sa, 64-\sa, \t
147	.endm
148
149	/* load 32-bit 'value' into 'reg' compensating for the ldil
150	* sign-extension when running in wide mode.
151	* WARNING!! neither 'value' nor 'reg' can be expressions
152	* containing '.'!!!! */
153	.macro load32 value, reg
154	ldil L%\value, \reg
155	ldo R%\value(\reg), \reg
156	.endm
157
158	.macro loadgp
159	#ifdef __LP64__
160	ldil L%__gp, %r27
161	ldo R%__gp(%r27), %r27
162	#else
163	ldil L%$global$, %r27
164	ldo R%$global$(%r27), %r27
165	#endif
166	.endm
167
168	#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
169	#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
170	#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
171	#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
172
173	.macro save_general regs
174	STREG %r1, PT_GR1 (\regs)
175	STREG %r2, PT_GR2 (\regs)
176	STREG %r3, PT_GR3 (\regs)
177	STREG %r4, PT_GR4 (\regs)
178	STREG %r5, PT_GR5 (\regs)
179	STREG %r6, PT_GR6 (\regs)
180	STREG %r7, PT_GR7 (\regs)
181	STREG %r8, PT_GR8 (\regs)
182	STREG %r9, PT_GR9 (\regs)
183	STREG %r10, PT_GR10(\regs)
184	STREG %r11, PT_GR11(\regs)
185	STREG %r12, PT_GR12(\regs)
186	STREG %r13, PT_GR13(\regs)
187	STREG %r14, PT_GR14(\regs)
188	STREG %r15, PT_GR15(\regs)
189	STREG %r16, PT_GR16(\regs)
190	STREG %r17, PT_GR17(\regs)
191	STREG %r18, PT_GR18(\regs)
192	STREG %r19, PT_GR19(\regs)
193	STREG %r20, PT_GR20(\regs)
194	STREG %r21, PT_GR21(\regs)
195	STREG %r22, PT_GR22(\regs)
196	STREG %r23, PT_GR23(\regs)
197	STREG %r24, PT_GR24(\regs)
198	STREG %r25, PT_GR25(\regs)
199	/* r26 is saved in get_stack and used to preserve a value across virt_map */
200	STREG %r27, PT_GR27(\regs)
201	STREG %r28, PT_GR28(\regs)
202	/* r29 is saved in get_stack and used to point to saved registers */
203	/* r30 stack pointer saved in get_stack */
204	STREG %r31, PT_GR31(\regs)
205	.endm
206
207	.macro rest_general regs
208	/* r1 used as a temp in rest_stack and is restored there */
209	LDREG PT_GR2 (\regs), %r2
210	LDREG PT_GR3 (\regs), %r3
211	LDREG PT_GR4 (\regs), %r4
212	LDREG PT_GR5 (\regs), %r5
213	LDREG PT_GR6 (\regs), %r6
214	LDREG PT_GR7 (\regs), %r7
215	LDREG PT_GR8 (\regs), %r8
216	LDREG PT_GR9 (\regs), %r9
217	LDREG PT_GR10(\regs), %r10
218	LDREG PT_GR11(\regs), %r11
219	LDREG PT_GR12(\regs), %r12
220	LDREG PT_GR13(\regs), %r13
221	LDREG PT_GR14(\regs), %r14
222	LDREG PT_GR15(\regs), %r15
223	LDREG PT_GR16(\regs), %r16
224	LDREG PT_GR17(\regs), %r17
225	LDREG PT_GR18(\regs), %r18
226	LDREG PT_GR19(\regs), %r19
227	LDREG PT_GR20(\regs), %r20
228	LDREG PT_GR21(\regs), %r21
229	LDREG PT_GR22(\regs), %r22
230	LDREG PT_GR23(\regs), %r23
231	LDREG PT_GR24(\regs), %r24
232	LDREG PT_GR25(\regs), %r25
233	LDREG PT_GR26(\regs), %r26
234	LDREG PT_GR27(\regs), %r27
235	LDREG PT_GR28(\regs), %r28
236	/* r29 points to register save area, and is restored in rest_stack */
237	/* r30 stack pointer restored in rest_stack */
238	LDREG PT_GR31(\regs), %r31
239	.endm
240
241	.macro save_fp regs
242	fstd,ma %fr0, 8(\regs)
243	fstd,ma %fr1, 8(\regs)
244	fstd,ma %fr2, 8(\regs)
245	fstd,ma %fr3, 8(\regs)
246	fstd,ma %fr4, 8(\regs)
247	fstd,ma %fr5, 8(\regs)
248	fstd,ma %fr6, 8(\regs)
249	fstd,ma %fr7, 8(\regs)
250	fstd,ma %fr8, 8(\regs)
251	fstd,ma %fr9, 8(\regs)
252	fstd,ma %fr10, 8(\regs)
253	fstd,ma %fr11, 8(\regs)
254	fstd,ma %fr12, 8(\regs)
255	fstd,ma %fr13, 8(\regs)
256	fstd,ma %fr14, 8(\regs)
257	fstd,ma %fr15, 8(\regs)
258	fstd,ma %fr16, 8(\regs)
259	fstd,ma %fr17, 8(\regs)
260	fstd,ma %fr18, 8(\regs)
261	fstd,ma %fr19, 8(\regs)
262	fstd,ma %fr20, 8(\regs)
263	fstd,ma %fr21, 8(\regs)
264	fstd,ma %fr22, 8(\regs)
265	fstd,ma %fr23, 8(\regs)
266	fstd,ma %fr24, 8(\regs)
267	fstd,ma %fr25, 8(\regs)
268	fstd,ma %fr26, 8(\regs)
269	fstd,ma %fr27, 8(\regs)
270	fstd,ma %fr28, 8(\regs)
271	fstd,ma %fr29, 8(\regs)
272	fstd,ma %fr30, 8(\regs)
273	fstd %fr31, 0(\regs)
274	.endm
275
276	.macro rest_fp regs
277	fldd 0(\regs), %fr31
278	fldd,mb -8(\regs), %fr30
279	fldd,mb -8(\regs), %fr29
280	fldd,mb -8(\regs), %fr28
281	fldd,mb -8(\regs), %fr27
282	fldd,mb -8(\regs), %fr26
283	fldd,mb -8(\regs), %fr25
284	fldd,mb -8(\regs), %fr24
285	fldd,mb -8(\regs), %fr23
286	fldd,mb -8(\regs), %fr22
287	fldd,mb -8(\regs), %fr21
288	fldd,mb -8(\regs), %fr20
289	fldd,mb -8(\regs), %fr19
290	fldd,mb -8(\regs), %fr18
291	fldd,mb -8(\regs), %fr17
292	fldd,mb -8(\regs), %fr16
293	fldd,mb -8(\regs), %fr15
294	fldd,mb -8(\regs), %fr14
295	fldd,mb -8(\regs), %fr13
296	fldd,mb -8(\regs), %fr12
297	fldd,mb -8(\regs), %fr11
298	fldd,mb -8(\regs), %fr10
299	fldd,mb -8(\regs), %fr9
300	fldd,mb -8(\regs), %fr8
301	fldd,mb -8(\regs), %fr7
302	fldd,mb -8(\regs), %fr6
303	fldd,mb -8(\regs), %fr5
304	fldd,mb -8(\regs), %fr4
305	fldd,mb -8(\regs), %fr3
306	fldd,mb -8(\regs), %fr2
307	fldd,mb -8(\regs), %fr1
308	fldd,mb -8(\regs), %fr0
309	.endm
310
618febd6 JB	311	.macro callee_save_float
	312	fstd,ma %fr12, 8(%r30)
	313	fstd,ma %fr13, 8(%r30)
	314	fstd,ma %fr14, 8(%r30)
	315	fstd,ma %fr15, 8(%r30)
	316	fstd,ma %fr16, 8(%r30)
	317	fstd,ma %fr17, 8(%r30)
	318	fstd,ma %fr18, 8(%r30)
	319	fstd,ma %fr19, 8(%r30)
	320	fstd,ma %fr20, 8(%r30)
	321	fstd,ma %fr21, 8(%r30)
	322	.endm
	323
	324	.macro callee_rest_float
	325	fldd,mb -8(%r30), %fr21
	326	fldd,mb -8(%r30), %fr20
	327	fldd,mb -8(%r30), %fr19
	328	fldd,mb -8(%r30), %fr18
	329	fldd,mb -8(%r30), %fr17
	330	fldd,mb -8(%r30), %fr16
	331	fldd,mb -8(%r30), %fr15
	332	fldd,mb -8(%r30), %fr14
	333	fldd,mb -8(%r30), %fr13
	334	fldd,mb -8(%r30), %fr12
	335	.endm
	336
1da177e4 LT	337	#ifdef __LP64__
1da177e4 LT	338	.macro callee_save
618febd6	339	std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
1da177e4 LT	340	mfctl %cr27, %r3
	341	std %r4, -136(%r30)
	342	std %r5, -128(%r30)
	343	std %r6, -120(%r30)
	344	std %r7, -112(%r30)
	345	std %r8, -104(%r30)
	346	std %r9, -96(%r30)
	347	std %r10, -88(%r30)
	348	std %r11, -80(%r30)
	349	std %r12, -72(%r30)
	350	std %r13, -64(%r30)
	351	std %r14, -56(%r30)
	352	std %r15, -48(%r30)
	353	std %r16, -40(%r30)
	354	std %r17, -32(%r30)
	355	std %r18, -24(%r30)
	356	std %r3, -16(%r30)
	357	.endm
	358
	359	.macro callee_rest
	360	ldd -16(%r30), %r3
	361	ldd -24(%r30), %r18
	362	ldd -32(%r30), %r17
	363	ldd -40(%r30), %r16
	364	ldd -48(%r30), %r15
	365	ldd -56(%r30), %r14
	366	ldd -64(%r30), %r13
	367	ldd -72(%r30), %r12
	368	ldd -80(%r30), %r11
	369	ldd -88(%r30), %r10
	370	ldd -96(%r30), %r9
	371	ldd -104(%r30), %r8
	372	ldd -112(%r30), %r7
	373	ldd -120(%r30), %r6
	374	ldd -128(%r30), %r5
	375	ldd -136(%r30), %r4
	376	mtctl %r3, %cr27
618febd6	377	ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
1da177e4 LT	378	.endm
	379
	380	#else /* ! __LP64__ */
	381
	382	.macro callee_save
618febd6	383	stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
1da177e4 LT	384	mfctl %cr27, %r3
	385	stw %r4, -124(%r30)
	386	stw %r5, -120(%r30)
	387	stw %r6, -116(%r30)
	388	stw %r7, -112(%r30)
	389	stw %r8, -108(%r30)
	390	stw %r9, -104(%r30)
	391	stw %r10, -100(%r30)
	392	stw %r11, -96(%r30)
	393	stw %r12, -92(%r30)
	394	stw %r13, -88(%r30)
	395	stw %r14, -84(%r30)
	396	stw %r15, -80(%r30)
	397	stw %r16, -76(%r30)
	398	stw %r17, -72(%r30)
	399	stw %r18, -68(%r30)
	400	stw %r3, -64(%r30)
	401	.endm
	402
	403	.macro callee_rest
	404	ldw -64(%r30), %r3
	405	ldw -68(%r30), %r18
	406	ldw -72(%r30), %r17
	407	ldw -76(%r30), %r16
	408	ldw -80(%r30), %r15
	409	ldw -84(%r30), %r14
	410	ldw -88(%r30), %r13
	411	ldw -92(%r30), %r12
	412	ldw -96(%r30), %r11
	413	ldw -100(%r30), %r10
	414	ldw -104(%r30), %r9
	415	ldw -108(%r30), %r8
	416	ldw -112(%r30), %r7
	417	ldw -116(%r30), %r6
	418	ldw -120(%r30), %r5
	419	ldw -124(%r30), %r4
	420	mtctl %r3, %cr27
618febd6	421	ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
1da177e4 LT	422	.endm
	423	#endif /* ! __LP64__ */
	424
	425	.macro save_specials regs
	426
	427	SAVE_SP (%sr0, PT_SR0 (\regs))
	428	SAVE_SP (%sr1, PT_SR1 (\regs))
	429	SAVE_SP (%sr2, PT_SR2 (\regs))
	430	SAVE_SP (%sr3, PT_SR3 (\regs))
	431	SAVE_SP (%sr4, PT_SR4 (\regs))
	432	SAVE_SP (%sr5, PT_SR5 (\regs))
	433	SAVE_SP (%sr6, PT_SR6 (\regs))
	434	SAVE_SP (%sr7, PT_SR7 (\regs))
	435
	436	SAVE_CR (%cr17, PT_IASQ0(\regs))
	437	mtctl %r0, %cr17
	438	SAVE_CR (%cr17, PT_IASQ1(\regs))
	439
	440	SAVE_CR (%cr18, PT_IAOQ0(\regs))
	441	mtctl %r0, %cr18
	442	SAVE_CR (%cr18, PT_IAOQ1(\regs))
	443
	444	#ifdef __LP64__
	445	/* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0
	446	* For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
	447	* reads 5 bits. Use mfctl,w to read all six bits. Otherwise
	448	* we lose the 6th bit on a save/restore over interrupt.
	449	*/
	450	mfctl,w %cr11, %r1
	451	STREG %r1, PT_SAR (\regs)
	452	#else
	453	SAVE_CR (%cr11, PT_SAR (\regs))
	454	#endif
	455	SAVE_CR (%cr19, PT_IIR (\regs))
	456
	457	/*
	458	* Code immediately following this macro (in intr_save) relies
	459	* on r8 containing ipsw.
	460	*/
	461	mfctl %cr22, %r8
	462	STREG %r8, PT_PSW(\regs)
	463	.endm
	464
	465	.macro rest_specials regs
	466
	467	REST_SP (%sr0, PT_SR0 (\regs))
	468	REST_SP (%sr1, PT_SR1 (\regs))
	469	REST_SP (%sr2, PT_SR2 (\regs))
	470	REST_SP (%sr3, PT_SR3 (\regs))
	471	REST_SP (%sr4, PT_SR4 (\regs))
	472	REST_SP (%sr5, PT_SR5 (\regs))
	473	REST_SP (%sr6, PT_SR6 (\regs))
	474	REST_SP (%sr7, PT_SR7 (\regs))
	475
	476	REST_CR (%cr17, PT_IASQ0(\regs))
	477	REST_CR (%cr17, PT_IASQ1(\regs))
	478
	479	REST_CR (%cr18, PT_IAOQ0(\regs))
	480	REST_CR (%cr18, PT_IAOQ1(\regs))
	481
	482	REST_CR (%cr11, PT_SAR (\regs))
	483
	484	REST_CR (%cr22, PT_PSW (\regs))
	485	.endm
486
896a3756 GG	487
	488	/* First step to create a "relied upon translation"
	489	* See PA 2.0 Arch. page F-4 and F-5.
	490	*
	491	* The ssm was originally necessary due to a "PCxT bug".
	492	* But someone decided it needed to be added to the architecture
	493	* and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
	494	* It's been carried forward into PA 2.0 Arch as well. :^(
	495	*
	496	* "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
	497	* rsm/ssm prevents the ifetch unit from speculatively fetching
	498	* instructions past this line in the code stream.
	499	* PA 2.0 processor will single step all insn in the same QUAD (4 insn).
	500	*/
	501	.macro pcxt_ssm_bug
	502	rsm PSW_SM_I,%r0
	503	nop /* 1 */
	504	nop /* 2 */
	505	nop /* 3 */
	506	nop /* 4 */
	507	nop /* 5 */
	508	nop /* 6 */
	509	nop /* 7 */
	510	.endm
	511
1da177e4 LT	512	#endif /* __ASSEMBLY__ */
1da177e4 LT	513	#endif