Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
78b09735 SR |
2 | * Copyright (C) 2004 IBM |
3 | * | |
4 | * Implements the generic device dma API for powerpc. | |
5 | * the pci and vio busses | |
1da177e4 | 6 | */ |
78b09735 SR |
7 | #ifndef _ASM_DMA_MAPPING_H |
8 | #define _ASM_DMA_MAPPING_H | |
33ff910f AB |
9 | #ifdef __KERNEL__ |
10 | ||
11 | #include <linux/types.h> | |
12 | #include <linux/cache.h> | |
13 | /* need struct page definitions */ | |
14 | #include <linux/mm.h> | |
15 | #include <linux/scatterlist.h> | |
16 | #include <asm/io.h> | |
17 | ||
18 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | |
19 | ||
20 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
21 | /* | |
22 | * DMA-consistent mapping functions for PowerPCs that don't support | |
23 | * cache snooping. These allocate/free a region of uncached mapped | |
24 | * memory space for use with DMA devices. Alternatively, you could | |
25 | * allocate the space "normally" and use the cache management functions | |
26 | * to ensure it is consistent. | |
27 | */ | |
28 | extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp); | |
29 | extern void __dma_free_coherent(size_t size, void *vaddr); | |
30 | extern void __dma_sync(void *vaddr, size_t size, int direction); | |
31 | extern void __dma_sync_page(struct page *page, unsigned long offset, | |
32 | size_t size, int direction); | |
33 | ||
34 | #else /* ! CONFIG_NOT_COHERENT_CACHE */ | |
35 | /* | |
36 | * Cache coherent cores. | |
37 | */ | |
38 | ||
39 | #define __dma_alloc_coherent(gfp, size, handle) NULL | |
40 | #define __dma_free_coherent(size, addr) ((void)0) | |
41 | #define __dma_sync(addr, size, rw) ((void)0) | |
42 | #define __dma_sync_page(pg, off, sz, rw) ((void)0) | |
43 | ||
44 | #endif /* ! CONFIG_NOT_COHERENT_CACHE */ | |
45 | ||
46 | #ifdef CONFIG_PPC64 | |
47 | /* | |
48 | * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO | |
49 | */ | |
50 | struct dma_mapping_ops { | |
51 | void * (*alloc_coherent)(struct device *dev, size_t size, | |
52 | dma_addr_t *dma_handle, gfp_t flag); | |
53 | void (*free_coherent)(struct device *dev, size_t size, | |
54 | void *vaddr, dma_addr_t dma_handle); | |
55 | dma_addr_t (*map_single)(struct device *dev, void *ptr, | |
56 | size_t size, enum dma_data_direction direction); | |
57 | void (*unmap_single)(struct device *dev, dma_addr_t dma_addr, | |
58 | size_t size, enum dma_data_direction direction); | |
59 | int (*map_sg)(struct device *dev, struct scatterlist *sg, | |
60 | int nents, enum dma_data_direction direction); | |
61 | void (*unmap_sg)(struct device *dev, struct scatterlist *sg, | |
62 | int nents, enum dma_data_direction direction); | |
63 | int (*dma_supported)(struct device *dev, u64 mask); | |
64 | int (*set_dma_mask)(struct device *dev, u64 dma_mask); | |
65 | }; | |
66 | ||
67 | static inline struct dma_mapping_ops *get_dma_ops(struct device *dev) | |
68 | { | |
69 | /* We don't handle the NULL dev case for ISA for now. We could | |
70 | * do it via an out of line call but it is not needed for now. The | |
71 | * only ISA DMA device we support is the floppy and we have a hack | |
72 | * in the floppy driver directly to get a device for us. | |
73 | */ | |
74 | if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL)) | |
75 | return NULL; | |
76 | return dev->archdata.dma_ops; | |
1f62a162 ME |
77 | } |
78 | ||
79 | static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops) | |
80 | { | |
81 | dev->archdata.dma_ops = ops; | |
33ff910f AB |
82 | } |
83 | ||
84 | static inline int dma_supported(struct device *dev, u64 mask) | |
85 | { | |
86 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
87 | ||
88 | if (unlikely(dma_ops == NULL)) | |
89 | return 0; | |
90 | if (dma_ops->dma_supported == NULL) | |
91 | return 1; | |
92 | return dma_ops->dma_supported(dev, mask); | |
93 | } | |
94 | ||
84631f37 ME |
95 | /* We have our own implementation of pci_set_dma_mask() */ |
96 | #define HAVE_ARCH_PCI_SET_DMA_MASK | |
97 | ||
33ff910f AB |
98 | static inline int dma_set_mask(struct device *dev, u64 dma_mask) |
99 | { | |
100 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
101 | ||
102 | if (unlikely(dma_ops == NULL)) | |
103 | return -EIO; | |
104 | if (dma_ops->set_dma_mask != NULL) | |
105 | return dma_ops->set_dma_mask(dev, dma_mask); | |
106 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
107 | return -EIO; | |
108 | *dev->dma_mask = dma_mask; | |
109 | return 0; | |
110 | } | |
111 | ||
112 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | |
113 | dma_addr_t *dma_handle, gfp_t flag) | |
114 | { | |
115 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
116 | ||
117 | BUG_ON(!dma_ops); | |
118 | return dma_ops->alloc_coherent(dev, size, dma_handle, flag); | |
119 | } | |
120 | ||
121 | static inline void dma_free_coherent(struct device *dev, size_t size, | |
122 | void *cpu_addr, dma_addr_t dma_handle) | |
123 | { | |
124 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
125 | ||
126 | BUG_ON(!dma_ops); | |
127 | dma_ops->free_coherent(dev, size, cpu_addr, dma_handle); | |
128 | } | |
129 | ||
130 | static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, | |
131 | size_t size, | |
132 | enum dma_data_direction direction) | |
133 | { | |
134 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
135 | ||
136 | BUG_ON(!dma_ops); | |
137 | return dma_ops->map_single(dev, cpu_addr, size, direction); | |
138 | } | |
139 | ||
140 | static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, | |
141 | size_t size, | |
142 | enum dma_data_direction direction) | |
143 | { | |
144 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
145 | ||
146 | BUG_ON(!dma_ops); | |
147 | dma_ops->unmap_single(dev, dma_addr, size, direction); | |
148 | } | |
149 | ||
150 | static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | |
151 | unsigned long offset, size_t size, | |
152 | enum dma_data_direction direction) | |
153 | { | |
154 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
155 | ||
156 | BUG_ON(!dma_ops); | |
157 | return dma_ops->map_single(dev, page_address(page) + offset, size, | |
158 | direction); | |
159 | } | |
12d04eef BH |
160 | |
161 | static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, | |
162 | size_t size, | |
163 | enum dma_data_direction direction) | |
164 | { | |
165 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
166 | ||
167 | BUG_ON(!dma_ops); | |
168 | dma_ops->unmap_single(dev, dma_address, size, direction); | |
169 | } | |
170 | ||
171 | static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, | |
172 | int nents, enum dma_data_direction direction) | |
173 | { | |
174 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
175 | ||
176 | BUG_ON(!dma_ops); | |
177 | return dma_ops->map_sg(dev, sg, nents, direction); | |
178 | } | |
179 | ||
180 | static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, | |
181 | int nhwentries, | |
182 | enum dma_data_direction direction) | |
183 | { | |
184 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | |
185 | ||
186 | BUG_ON(!dma_ops); | |
187 | dma_ops->unmap_sg(dev, sg, nhwentries, direction); | |
188 | } | |
78b09735 | 189 | |
12d04eef BH |
190 | |
191 | /* | |
192 | * Available generic sets of operations | |
193 | */ | |
194 | extern struct dma_mapping_ops dma_iommu_ops; | |
195 | extern struct dma_mapping_ops dma_direct_ops; | |
78b09735 SR |
196 | |
197 | #else /* CONFIG_PPC64 */ | |
198 | ||
1da177e4 LT |
199 | #define dma_supported(dev, mask) (1) |
200 | ||
201 | static inline int dma_set_mask(struct device *dev, u64 dma_mask) | |
202 | { | |
203 | if (!dev->dma_mask || !dma_supported(dev, mask)) | |
204 | return -EIO; | |
205 | ||
206 | *dev->dma_mask = dma_mask; | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | |
d27477c2 | 212 | dma_addr_t * dma_handle, |
dd0fc66f | 213 | gfp_t gfp) |
1da177e4 LT |
214 | { |
215 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
216 | return __dma_alloc_coherent(size, dma_handle, gfp); | |
217 | #else | |
218 | void *ret; | |
219 | /* ignore region specifiers */ | |
220 | gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); | |
221 | ||
222 | if (dev == NULL || dev->coherent_dma_mask < 0xffffffff) | |
223 | gfp |= GFP_DMA; | |
224 | ||
225 | ret = (void *)__get_free_pages(gfp, get_order(size)); | |
226 | ||
227 | if (ret != NULL) { | |
228 | memset(ret, 0, size); | |
229 | *dma_handle = virt_to_bus(ret); | |
230 | } | |
231 | ||
232 | return ret; | |
233 | #endif | |
234 | } | |
235 | ||
236 | static inline void | |
237 | dma_free_coherent(struct device *dev, size_t size, void *vaddr, | |
238 | dma_addr_t dma_handle) | |
239 | { | |
240 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
241 | __dma_free_coherent(size, vaddr); | |
242 | #else | |
243 | free_pages((unsigned long)vaddr, get_order(size)); | |
244 | #endif | |
245 | } | |
246 | ||
247 | static inline dma_addr_t | |
248 | dma_map_single(struct device *dev, void *ptr, size_t size, | |
249 | enum dma_data_direction direction) | |
250 | { | |
251 | BUG_ON(direction == DMA_NONE); | |
252 | ||
253 | __dma_sync(ptr, size, direction); | |
254 | ||
255 | return virt_to_bus(ptr); | |
256 | } | |
257 | ||
f774216d SB |
258 | static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, |
259 | size_t size, | |
260 | enum dma_data_direction direction) | |
261 | { | |
262 | /* We do nothing. */ | |
263 | } | |
1da177e4 LT |
264 | |
265 | static inline dma_addr_t | |
266 | dma_map_page(struct device *dev, struct page *page, | |
267 | unsigned long offset, size_t size, | |
268 | enum dma_data_direction direction) | |
269 | { | |
270 | BUG_ON(direction == DMA_NONE); | |
271 | ||
272 | __dma_sync_page(page, offset, size, direction); | |
273 | ||
9f6a3d08 | 274 | return page_to_bus(page) + offset; |
1da177e4 LT |
275 | } |
276 | ||
f774216d SB |
277 | static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, |
278 | size_t size, | |
279 | enum dma_data_direction direction) | |
280 | { | |
281 | /* We do nothing. */ | |
282 | } | |
1da177e4 LT |
283 | |
284 | static inline int | |
78bdc310 | 285 | dma_map_sg(struct device *dev, struct scatterlist *sgl, int nents, |
1da177e4 LT |
286 | enum dma_data_direction direction) |
287 | { | |
78bdc310 | 288 | struct scatterlist *sg; |
1da177e4 LT |
289 | int i; |
290 | ||
291 | BUG_ON(direction == DMA_NONE); | |
292 | ||
78bdc310 | 293 | for_each_sg(sgl, sg, nents, i) { |
5edadbd0 OJ |
294 | BUG_ON(!sg_page(sg)); |
295 | __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction); | |
296 | sg->dma_address = page_to_bus(sg_page(sg)) + sg->offset; | |
1da177e4 LT |
297 | } |
298 | ||
299 | return nents; | |
300 | } | |
301 | ||
f774216d SB |
302 | static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, |
303 | int nhwentries, | |
304 | enum dma_data_direction direction) | |
305 | { | |
306 | /* We don't do anything here. */ | |
307 | } | |
1da177e4 | 308 | |
78b09735 SR |
309 | #endif /* CONFIG_PPC64 */ |
310 | ||
311 | static inline void dma_sync_single_for_cpu(struct device *dev, | |
312 | dma_addr_t dma_handle, size_t size, | |
313 | enum dma_data_direction direction) | |
1da177e4 LT |
314 | { |
315 | BUG_ON(direction == DMA_NONE); | |
1da177e4 LT |
316 | __dma_sync(bus_to_virt(dma_handle), size, direction); |
317 | } | |
318 | ||
78b09735 SR |
319 | static inline void dma_sync_single_for_device(struct device *dev, |
320 | dma_addr_t dma_handle, size_t size, | |
321 | enum dma_data_direction direction) | |
1da177e4 LT |
322 | { |
323 | BUG_ON(direction == DMA_NONE); | |
1da177e4 LT |
324 | __dma_sync(bus_to_virt(dma_handle), size, direction); |
325 | } | |
326 | ||
78b09735 | 327 | static inline void dma_sync_sg_for_cpu(struct device *dev, |
78bdc310 | 328 | struct scatterlist *sgl, int nents, |
78b09735 | 329 | enum dma_data_direction direction) |
1da177e4 | 330 | { |
78bdc310 | 331 | struct scatterlist *sg; |
1da177e4 LT |
332 | int i; |
333 | ||
334 | BUG_ON(direction == DMA_NONE); | |
335 | ||
78bdc310 | 336 | for_each_sg(sgl, sg, nents, i) |
5edadbd0 | 337 | __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction); |
1da177e4 LT |
338 | } |
339 | ||
78b09735 | 340 | static inline void dma_sync_sg_for_device(struct device *dev, |
78bdc310 | 341 | struct scatterlist *sgl, int nents, |
78b09735 | 342 | enum dma_data_direction direction) |
1da177e4 | 343 | { |
78bdc310 | 344 | struct scatterlist *sg; |
1da177e4 LT |
345 | int i; |
346 | ||
347 | BUG_ON(direction == DMA_NONE); | |
348 | ||
78bdc310 | 349 | for_each_sg(sgl, sg, nents, i) |
5edadbd0 | 350 | __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction); |
1da177e4 LT |
351 | } |
352 | ||
78b09735 SR |
353 | static inline int dma_mapping_error(dma_addr_t dma_addr) |
354 | { | |
355 | #ifdef CONFIG_PPC64 | |
356 | return (dma_addr == DMA_ERROR_CODE); | |
357 | #else | |
358 | return 0; | |
359 | #endif | |
360 | } | |
361 | ||
1da177e4 LT |
362 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) |
363 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | |
364 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
f67637ee | 365 | #define dma_is_consistent(d, h) (0) |
1da177e4 | 366 | #else |
f67637ee | 367 | #define dma_is_consistent(d, h) (1) |
1da177e4 LT |
368 | #endif |
369 | ||
370 | static inline int dma_get_cache_alignment(void) | |
371 | { | |
78b09735 SR |
372 | #ifdef CONFIG_PPC64 |
373 | /* no easy way to get cache size on all processors, so return | |
374 | * the maximum possible, to be safe */ | |
1fd73c6b | 375 | return (1 << INTERNODE_CACHE_SHIFT); |
78b09735 | 376 | #else |
1da177e4 LT |
377 | /* |
378 | * Each processor family will define its own L1_CACHE_SHIFT, | |
379 | * L1_CACHE_BYTES wraps to this, so this is always safe. | |
380 | */ | |
381 | return L1_CACHE_BYTES; | |
78b09735 | 382 | #endif |
1da177e4 LT |
383 | } |
384 | ||
78b09735 SR |
385 | static inline void dma_sync_single_range_for_cpu(struct device *dev, |
386 | dma_addr_t dma_handle, unsigned long offset, size_t size, | |
387 | enum dma_data_direction direction) | |
1da177e4 LT |
388 | { |
389 | /* just sync everything for now */ | |
390 | dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction); | |
391 | } | |
392 | ||
78b09735 SR |
393 | static inline void dma_sync_single_range_for_device(struct device *dev, |
394 | dma_addr_t dma_handle, unsigned long offset, size_t size, | |
395 | enum dma_data_direction direction) | |
1da177e4 LT |
396 | { |
397 | /* just sync everything for now */ | |
398 | dma_sync_single_for_device(dev, dma_handle, offset + size, direction); | |
399 | } | |
400 | ||
d3fa72e4 | 401 | static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
78b09735 | 402 | enum dma_data_direction direction) |
1da177e4 | 403 | { |
78b09735 | 404 | BUG_ON(direction == DMA_NONE); |
1da177e4 LT |
405 | __dma_sync(vaddr, size, (int)direction); |
406 | } | |
407 | ||
88ced031 | 408 | #endif /* __KERNEL__ */ |
78b09735 | 409 | #endif /* _ASM_DMA_MAPPING_H */ |