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1da177e4 LT |
1 | /* |
2 | * lppaca.h | |
3 | * Copyright (C) 2001 Mike Corrigan IBM Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
8882a4da DG |
19 | #ifndef _ASM_POWERPC_LPPACA_H |
20 | #define _ASM_POWERPC_LPPACA_H | |
88ced031 | 21 | #ifdef __KERNEL__ |
1da177e4 LT |
22 | |
23 | //============================================================================= | |
24 | // | |
25 | // This control block contains the data that is shared between the | |
26 | // hypervisor (PLIC) and the OS. | |
27 | // | |
28 | // | |
29 | //---------------------------------------------------------------------------- | |
2f6093c8 | 30 | #include <linux/cache.h> |
1da177e4 | 31 | #include <asm/types.h> |
2f6093c8 | 32 | #include <asm/mmu.h> |
1da177e4 | 33 | |
3356bb9f DG |
34 | /* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k |
35 | * alignment is sufficient to prevent this */ | |
c6b3feaf | 36 | struct lppaca { |
1da177e4 LT |
37 | //============================================================================= |
38 | // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data | |
39 | // NOTE: The xDynXyz fields are fields that will be dynamically changed by | |
40 | // PLIC when preparing to bring a processor online or when dispatching a | |
41 | // virtual processor! | |
42 | //============================================================================= | |
43 | u32 desc; // Eye catcher 0xD397D781 x00-x03 | |
44 | u16 size; // Size of this struct x04-x05 | |
45 | u16 reserved1; // Reserved x06-x07 | |
46 | u16 reserved2:14; // Reserved x08-x09 | |
47 | u8 shared_proc:1; // Shared processor indicator ... | |
48 | u8 secondary_thread:1; // Secondary thread indicator ... | |
49 | volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A | |
50 | u8 secondary_thread_count; // Secondary thread count x0B-x0B | |
51 | volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D | |
52 | volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F | |
53 | u32 decr_val; // Value for Decr programming x10-x13 | |
54 | u32 pmc_val; // Value for PMC regs x14-x17 | |
55 | volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B | |
56 | volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F | |
57 | volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23 | |
58 | u32 dsei_data; // DSEI data x24-x27 | |
59 | u64 sprg3; // SPRG3 value x28-x2F | |
60 | u8 reserved3[80]; // Reserved x30-x7F | |
61 | ||
62 | //============================================================================= | |
63 | // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data | |
64 | //============================================================================= | |
65 | // This Dword contains a byte for each type of interrupt that can occur. | |
66 | // The IPI is a count while the others are just a binary 1 or 0. | |
67 | union { | |
68 | u64 any_int; | |
69 | struct { | |
70 | u16 reserved; // Reserved - cleared by #mpasmbl | |
71 | u8 xirr_int; // Indicates xXirrValue is valid or Immed IO | |
72 | u8 ipi_cnt; // IPI Count | |
73 | u8 decr_int; // DECR interrupt occurred | |
74 | u8 pdc_int; // PDC interrupt occurred | |
75 | u8 quantum_int; // Interrupt quantum reached | |
76 | u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending | |
77 | } fields; | |
78 | } int_dword; | |
79 | ||
80 | // Whenever any fields in this Dword are set then PLIC will defer the | |
81 | // processing of external interrupts. Note that PLIC will store the | |
82 | // XIRR directly into the xXirrValue field so that another XIRR will | |
83 | // not be presented until this one clears. The layout of the low | |
84 | // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the | |
85 | // entire Dword is zero or not. A non-zero value in the low order | |
86 | // 2-bytes will result in SLIC being granted the highest thread | |
87 | // priority upon return. A 0 will return to SLIC as medium priority. | |
88 | u64 plic_defer_ints_area; // Entire Dword | |
89 | ||
90 | // Used to pass the real SRR0/1 from PLIC to SLIC as well as to | |
91 | // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid. | |
92 | u64 saved_srr0; // Saved SRR0 x10-x17 | |
93 | u64 saved_srr1; // Saved SRR1 x18-x1F | |
94 | ||
95 | // Used to pass parms from the OS to PLIC for SetAsrAndRfid | |
96 | u64 saved_gpr3; // Saved GPR3 x20-x27 | |
97 | u64 saved_gpr4; // Saved GPR4 x28-x2F | |
98 | u64 saved_gpr5; // Saved GPR5 x30-x37 | |
99 | ||
100 | u8 reserved4; // Reserved x38-x38 | |
d8c391a5 | 101 | u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 |
1da177e4 LT |
102 | u8 fpregs_in_use; // FP regs in use x3A-x3A |
103 | u8 pmcregs_in_use; // PMC regs in use x3B-x3B | |
104 | volatile u32 saved_decr; // Saved Decr Value x3C-x3F | |
105 | volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47 | |
106 | volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F | |
107 | u64 tot_plic_latency; // Accumulated PLIC latency x50-x57 | |
108 | u64 wait_state_cycles; // Wait cycles for this proc x58-x5F | |
109 | u64 end_of_quantum; // TB at end of quantum x60-x67 | |
110 | u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F | |
111 | u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77 | |
112 | volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B | |
113 | u16 slb_count; // # of SLBs to maintain x7C-x7D | |
114 | u8 idle; // Indicate OS is idle x7E | |
233ccd0d | 115 | u8 vmxregs_in_use; // VMX registers in use x7F |
1da177e4 LT |
116 | |
117 | ||
118 | //============================================================================= | |
5cf13911 | 119 | // CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors |
1da177e4 LT |
120 | //============================================================================= |
121 | // This is the yield_count. An "odd" value (low bit on) means that | |
122 | // the processor is yielded (either because of an OS yield or a PLIC | |
123 | // preempt). An even value implies that the processor is currently | |
124 | // executing. | |
125 | // NOTE: This value will ALWAYS be zero for dedicated processors and | |
126 | // will NEVER be zero for shared processors (ie, initialized to a 1). | |
127 | volatile u32 yield_count; // PLIC increments each dispatchx00-x03 | |
128 | u8 reserved6[124]; // Reserved x04-x7F | |
129 | ||
130 | //============================================================================= | |
5cf13911 | 131 | // CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data |
1da177e4 LT |
132 | //============================================================================= |
133 | u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF | |
c6b3feaf | 134 | } __attribute__((__aligned__(0x400))); |
1da177e4 | 135 | |
3356bb9f DG |
136 | extern struct lppaca lppaca[]; |
137 | ||
2f6093c8 MN |
138 | /* |
139 | * SLB shadow buffer structure as defined in the PAPR. The save_area | |
140 | * contains adjacent ESID and VSID pairs for each shadowed SLB. The | |
141 | * ESID is stored in the lower 64bits, then the VSID. | |
142 | */ | |
143 | struct slb_shadow { | |
144 | u32 persistent; // Number of persistent SLBs x00-x03 | |
145 | u32 buffer_length; // Total shadow buffer length x04-x07 | |
146 | u64 reserved; // Alignment x08-x0f | |
147 | struct { | |
148 | u64 esid; | |
149 | u64 vsid; | |
150 | } save_area[SLB_NUM_BOLTED]; // x10-x40 | |
151 | } ____cacheline_aligned; | |
152 | ||
153 | extern struct slb_shadow slb_shadow[]; | |
154 | ||
88ced031 | 155 | #endif /* __KERNEL__ */ |
8882a4da | 156 | #endif /* _ASM_POWERPC_LPPACA_H */ |