[deliverable/linux.git] / include / asm-powerpc / pgtable-64k.h

#ifndef _ASM_POWERPC_PGTABLE_64K_H
#define _ASM_POWERPC_PGTABLE_64K_H

#include <asm-generic/pgtable-nopud.h>


#define PTE_INDEX_SIZE  12
#define PMD_INDEX_SIZE  12
#define PUD_INDEX_SIZE	0
#define PGD_INDEX_SIZE  4

#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE	(sizeof(real_pte_t) << PTE_INDEX_SIZE)
#define PMD_TABLE_SIZE	(sizeof(pmd_t) << PMD_INDEX_SIZE)
#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
#endif	/* __ASSEMBLY__ */

#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)

/* With 4k base page size, hugepage PTEs go at the PMD level */
#define MIN_HUGEPTE_SHIFT	PAGE_SHIFT

/* PMD_SHIFT determines what a second-level page table entry can map */
#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))

/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/* Additional PTE bits (don't change without checking asm in hash_low.S) */
#define _PAGE_HPTE_SUB	0x0ffff000 /* combo only: sub pages HPTE bits */
#define _PAGE_HPTE_SUB0	0x08000000 /* combo only: first sub page */
#define _PAGE_COMBO	0x10000000 /* this is a combo 4k page */
#define _PAGE_4K_PFN	0x20000000 /* PFN is for a single 4k page */

/* Note the full page bits must be in the same location as for normal
 * 4k pages as the same asssembly will be used to insert 64K pages
 * wether the kernel has CONFIG_PPC_64K_PAGES or not
 */
#define _PAGE_F_SECOND  0x00008000 /* full page: hidx bits */
#define _PAGE_F_GIX     0x00007000 /* full page: hidx bits */

/* PTE flags to conserve for HPTE identification */
#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
                         _PAGE_COMBO)

/* Shift to put page number into pte.
 *
 * That gives us a max RPN of 34 bits, which means a max of 50 bits
 * of addressable physical space, or 46 bits for the special 4k PFNs.
 */
#define PTE_RPN_SHIFT	(30)
#define PTE_RPN_MAX	(1UL << (64 - PTE_RPN_SHIFT))
#define PTE_RPN_MASK	(~((1UL<<PTE_RPN_SHIFT)-1))

/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
 * pgprot changes
 */
#define _PAGE_CHG_MASK	(PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
                         _PAGE_ACCESSED)

/* Bits to mask out from a PMD to get to the PTE page */
#define PMD_MASKED_BITS		0x1ff
/* Bits to mask out from a PGD/PUD to get to the PMD page */
#define PUD_MASKED_BITS		0x1ff

/* Manipulate "rpte" values */
#define __real_pte(e,p) 	((real_pte_t) { \
	(e), pte_val(*((p) + PTRS_PER_PTE)) })
#define __rpte_to_hidx(r,index)	((pte_val((r).pte) & _PAGE_COMBO) ? \
        (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
#define __rpte_to_pte(r)	((r).pte)
#define __rpte_sub_valid(rpte, index) \
	(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))


/* Trick: we set __end to va + 64k, which happens works for
 * a 16M page as well as we want only one iteration
 */
#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)	    \
        do {                                                                \
                unsigned long __end = va + PAGE_SIZE;                       \
                unsigned __split = (psize == MMU_PAGE_4K ||                 \
				    psize == MMU_PAGE_64K_AP);              \
                shift = mmu_psize_defs[psize].shift;                        \
	        for (index = 0; va < __end; index++, va += (1 << shift)) {  \
		        if (!__split || __rpte_sub_valid(rpte, index)) do { \

#define pte_iterate_hashed_end() } while(0); } } while(0)

#define pte_pagesize_index(mm, addr, pte)	\
	(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)

#define remap_4k_pfn(vma, addr, pfn, prot)				\
	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,		\
			__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))

#endif /* _ASM_POWERPC_PGTABLE_64K_H */
Commit	Line	Data
88ced031 AB	1	#ifndef _ASM_POWERPC_PGTABLE_64K_H
88ced031 AB	2	#define _ASM_POWERPC_PGTABLE_64K_H
88ced031	3
3c726f8d BH	4	#include <asm-generic/pgtable-nopud.h>
	5
	6
	7	#define PTE_INDEX_SIZE 12
	8	#define PMD_INDEX_SIZE 12
	9	#define PUD_INDEX_SIZE 0
	10	#define PGD_INDEX_SIZE 4
	11
ee7a76da	12	#ifndef __ASSEMBLY__
3c726f8d BH	13	#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
	14	#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
	15	#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
ee7a76da	16	#endif /* __ASSEMBLY__ */
3c726f8d BH	17
	18	#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
	19	#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
	20	#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
	21
7d24f0b8 DG	22	/* With 4k base page size, hugepage PTEs go at the PMD level */
	23	#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
	24
3c726f8d BH	25	/* PMD_SHIFT determines what a second-level page table entry can map */
	26	#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
	27	#define PMD_SIZE (1UL << PMD_SHIFT)
	28	#define PMD_MASK (~(PMD_SIZE-1))
	29
	30	/* PGDIR_SHIFT determines what a third-level page table entry can map */
	31	#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
	32	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	33	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	34
	35	/* Additional PTE bits (don't change without checking asm in hash_low.S) */
	36	#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
	37	#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
	38	#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
721151d0	39	#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
16c2d476 BH	40
	41	/* Note the full page bits must be in the same location as for normal
	42	* 4k pages as the same asssembly will be used to insert 64K pages
	43	* wether the kernel has CONFIG_PPC_64K_PAGES or not
	44	*/
3c726f8d BH	45	#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
	46	#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
	47
	48	/* PTE flags to conserve for HPTE identification */
	49	#define _PAGE_HPTEFLAGS (_PAGE_BUSY \| _PAGE_HASHPTE \| _PAGE_HPTE_SUB \|\
	50	_PAGE_COMBO)
	51
	52	/* Shift to put page number into pte.
	53	*
c0f7c6cb PM	54	* That gives us a max RPN of 34 bits, which means a max of 50 bits
c0f7c6cb PM	55	* of addressable physical space, or 46 bits for the special 4k PFNs.
3c726f8d	56	*/
c0f7c6cb	57	#define PTE_RPN_SHIFT (30)
3c726f8d BH	58	#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
	59	#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
	60
	61	/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
	62	* pgprot changes
	63	*/
	64	#define _PAGE_CHG_MASK (PTE_RPN_MASK \| _PAGE_HPTEFLAGS \| _PAGE_DIRTY \| \
	65	_PAGE_ACCESSED)
	66
	67	/* Bits to mask out from a PMD to get to the PTE page */
	68	#define PMD_MASKED_BITS 0x1ff
	69	/* Bits to mask out from a PGD/PUD to get to the PMD page */
	70	#define PUD_MASKED_BITS 0x1ff
	71
3c726f8d BH	72	/* Manipulate "rpte" values */
	73	#define __real_pte(e,p) ((real_pte_t) { \
	74	(e), pte_val(*((p) + PTRS_PER_PTE)) })
	75	#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
	76	(((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
	77	#define __rpte_to_pte(r) ((r).pte)
	78	#define __rpte_sub_valid(rpte, index) \
	79	(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
	80
	81
	82	/* Trick: we set __end to va + 64k, which happens works for
	83	* a 16M page as well as we want only one iteration
	84	*/
	85	#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
	86	do { \
	87	unsigned long __end = va + PAGE_SIZE; \
	88	unsigned __split = (psize == MMU_PAGE_4K \|\| \
	89	psize == MMU_PAGE_64K_AP); \
	90	shift = mmu_psize_defs[psize].shift; \
	91	for (index = 0; va < __end; index++, va += (1 << shift)) { \
	92	if (!__split \|\| __rpte_sub_valid(rpte, index)) do { \
	93
	94	#define pte_iterate_hashed_end() } while(0); } } while(0)
	95
16c2d476	96	#define pte_pagesize_index(mm, addr, pte) \
bf72aeba	97	(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
3c726f8d	98
721151d0 PM	99	#define remap_4k_pfn(vma, addr, pfn, prot) \
	100	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
	101	__pgprot(pgprot_val((prot)) \| _PAGE_4K_PFN))
	102
88ced031	103	#endif /* _ASM_POWERPC_PGTABLE_64K_H */