Commit | Line | Data |
---|---|---|
98658538 LY |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. | |
3 | * | |
4 | * Authors: Shlomi Gridish <gridish@freescale.com> | |
5 | * Li Yang <leoli@freescale.com> | |
6 | * | |
7 | * Description: | |
8 | * Internal header file for UCC SLOW unit routines. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | #ifndef __UCC_SLOW_H__ | |
16 | #define __UCC_SLOW_H__ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | ||
20 | #include <asm/immap_qe.h> | |
21 | #include <asm/qe.h> | |
22 | ||
23 | #include "ucc.h" | |
24 | ||
25 | /* transmit BD's status */ | |
26 | #define T_R 0x80000000 /* ready bit */ | |
27 | #define T_PAD 0x40000000 /* add pads to short frames */ | |
28 | #define T_W 0x20000000 /* wrap bit */ | |
29 | #define T_I 0x10000000 /* interrupt on completion */ | |
30 | #define T_L 0x08000000 /* last */ | |
31 | ||
32 | #define T_A 0x04000000 /* Address - the data transmitted as address | |
33 | chars */ | |
34 | #define T_TC 0x04000000 /* transmit CRC */ | |
35 | #define T_CM 0x02000000 /* continuous mode */ | |
36 | #define T_DEF 0x02000000 /* collision on previous attempt to transmit */ | |
37 | #define T_P 0x01000000 /* Preamble - send Preamble sequence before | |
38 | data */ | |
39 | #define T_HB 0x01000000 /* heartbeat */ | |
40 | #define T_NS 0x00800000 /* No Stop */ | |
41 | #define T_LC 0x00800000 /* late collision */ | |
42 | #define T_RL 0x00400000 /* retransmission limit */ | |
43 | #define T_UN 0x00020000 /* underrun */ | |
44 | #define T_CT 0x00010000 /* CTS lost */ | |
45 | #define T_CSL 0x00010000 /* carrier sense lost */ | |
46 | #define T_RC 0x003c0000 /* retry count */ | |
47 | ||
48 | /* Receive BD's status */ | |
49 | #define R_E 0x80000000 /* buffer empty */ | |
50 | #define R_W 0x20000000 /* wrap bit */ | |
51 | #define R_I 0x10000000 /* interrupt on reception */ | |
52 | #define R_L 0x08000000 /* last */ | |
53 | #define R_C 0x08000000 /* the last byte in this buffer is a cntl | |
54 | char */ | |
55 | #define R_F 0x04000000 /* first */ | |
56 | #define R_A 0x04000000 /* the first byte in this buffer is address | |
57 | byte */ | |
58 | #define R_CM 0x02000000 /* continuous mode */ | |
59 | #define R_ID 0x01000000 /* buffer close on reception of idles */ | |
60 | #define R_M 0x01000000 /* Frame received because of promiscuous | |
61 | mode */ | |
62 | #define R_AM 0x00800000 /* Address match */ | |
63 | #define R_DE 0x00800000 /* Address match */ | |
64 | #define R_LG 0x00200000 /* Break received */ | |
65 | #define R_BR 0x00200000 /* Frame length violation */ | |
66 | #define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */ | |
67 | #define R_FR 0x00100000 /* Framing Error (no stop bit) character | |
68 | received */ | |
69 | #define R_PR 0x00080000 /* Parity Error character received */ | |
70 | #define R_AB 0x00080000 /* Frame Aborted */ | |
71 | #define R_SH 0x00080000 /* frame is too short */ | |
72 | #define R_CR 0x00040000 /* CRC Error */ | |
73 | #define R_OV 0x00020000 /* Overrun */ | |
74 | #define R_CD 0x00010000 /* CD lost */ | |
75 | #define R_CL 0x00010000 /* this frame is closed because of a | |
76 | collision */ | |
77 | ||
78 | /* Rx Data buffer must be 4 bytes aligned in most cases.*/ | |
79 | #define UCC_SLOW_RX_ALIGN 4 | |
80 | #define UCC_SLOW_MRBLR_ALIGNMENT 4 | |
81 | #define UCC_SLOW_PRAM_SIZE 0x100 | |
82 | #define ALIGNMENT_OF_UCC_SLOW_PRAM 64 | |
83 | ||
84 | /* UCC Slow Channel Protocol Mode */ | |
85 | enum ucc_slow_channel_protocol_mode { | |
86 | UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002, | |
87 | UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004, | |
88 | UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008, | |
89 | }; | |
90 | ||
91 | /* UCC Slow Transparent Transmit CRC (TCRC) */ | |
92 | enum ucc_slow_transparent_tcrc { | |
93 | /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */ | |
94 | UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000, | |
95 | /* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */ | |
96 | UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000, | |
97 | /* 32-bit CCITT CRC (Ethernet and HDLC) */ | |
98 | UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000, | |
99 | }; | |
100 | ||
101 | /* UCC Slow oversampling rate for transmitter (TDCR) */ | |
102 | enum ucc_slow_tx_oversampling_rate { | |
103 | /* 1x clock mode */ | |
104 | UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000, | |
105 | /* 8x clock mode */ | |
106 | UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000, | |
107 | /* 16x clock mode */ | |
108 | UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000, | |
109 | /* 32x clock mode */ | |
110 | UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000, | |
111 | }; | |
112 | ||
113 | /* UCC Slow Oversampling rate for receiver (RDCR) | |
114 | */ | |
115 | enum ucc_slow_rx_oversampling_rate { | |
116 | /* 1x clock mode */ | |
117 | UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000, | |
118 | /* 8x clock mode */ | |
119 | UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000, | |
120 | /* 16x clock mode */ | |
121 | UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000, | |
122 | /* 32x clock mode */ | |
123 | UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000, | |
124 | }; | |
125 | ||
126 | /* UCC Slow Transmitter encoding method (TENC) | |
127 | */ | |
128 | enum ucc_slow_tx_encoding_method { | |
129 | UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000, | |
130 | UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100 | |
131 | }; | |
132 | ||
133 | /* UCC Slow Receiver decoding method (RENC) | |
134 | */ | |
135 | enum ucc_slow_rx_decoding_method { | |
136 | UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000, | |
137 | UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800 | |
138 | }; | |
139 | ||
140 | /* UCC Slow Diagnostic mode (DIAG) | |
141 | */ | |
142 | enum ucc_slow_diag_mode { | |
143 | UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000, | |
144 | UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040, | |
145 | UCC_SLOW_DIAG_MODE_ECHO = 0x00000080, | |
146 | UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0 | |
147 | }; | |
148 | ||
149 | struct ucc_slow_info { | |
150 | int ucc_num; | |
151 | enum qe_clock rx_clock; | |
152 | enum qe_clock tx_clock; | |
153 | struct ucc_slow *us_regs; | |
154 | int irq; | |
155 | u16 uccm_mask; | |
156 | int data_mem_part; | |
157 | int init_tx; | |
158 | int init_rx; | |
159 | u32 tx_bd_ring_len; | |
160 | u32 rx_bd_ring_len; | |
161 | int rx_interrupts; | |
162 | int brkpt_support; | |
163 | int grant_support; | |
164 | int tsa; | |
165 | int cdp; | |
166 | int cds; | |
167 | int ctsp; | |
168 | int ctss; | |
169 | int rinv; | |
170 | int tinv; | |
171 | int rtsm; | |
172 | int rfw; | |
173 | int tci; | |
174 | int tend; | |
175 | int tfl; | |
176 | int txsy; | |
177 | u16 max_rx_buf_length; | |
178 | enum ucc_slow_transparent_tcrc tcrc; | |
179 | enum ucc_slow_channel_protocol_mode mode; | |
180 | enum ucc_slow_diag_mode diag; | |
181 | enum ucc_slow_tx_oversampling_rate tdcr; | |
182 | enum ucc_slow_rx_oversampling_rate rdcr; | |
183 | enum ucc_slow_tx_encoding_method tenc; | |
184 | enum ucc_slow_rx_decoding_method renc; | |
185 | }; | |
186 | ||
187 | struct ucc_slow_private { | |
188 | struct ucc_slow_info *us_info; | |
189 | struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs */ | |
190 | struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */ | |
191 | u32 us_pram_offset; | |
192 | int enabled_tx; /* Whether channel is enabled for Tx (ENT) */ | |
193 | int enabled_rx; /* Whether channel is enabled for Rx (ENR) */ | |
194 | int stopped_tx; /* Whether channel has been stopped for Tx | |
195 | (STOP_TX, etc.) */ | |
196 | int stopped_rx; /* Whether channel has been stopped for Rx */ | |
197 | struct list_head confQ; /* frames passed to chip waiting for tx */ | |
198 | u32 first_tx_bd_mask; /* mask is used in Tx routine to save status | |
199 | and length for first BD in a frame */ | |
200 | u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */ | |
201 | u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */ | |
202 | u8 *confBd; /* next BD for confirm after Tx */ | |
203 | u8 *tx_bd; /* next BD for new Tx request */ | |
204 | u8 *rx_bd; /* next BD to collect after Rx */ | |
205 | void *p_rx_frame; /* accumulating receive frame */ | |
206 | u16 *p_ucce; /* a pointer to the event register in memory. | |
207 | */ | |
208 | u16 *p_uccm; /* a pointer to the mask register in memory */ | |
209 | u16 saved_uccm; /* a saved mask for the RX Interrupt bits */ | |
210 | #ifdef STATISTICS | |
211 | u32 tx_frames; /* Transmitted frames counters */ | |
212 | u32 rx_frames; /* Received frames counters (only frames | |
213 | passed to application) */ | |
214 | u32 rx_discarded; /* Discarded frames counters (frames that | |
215 | were discarded by the driver due to | |
216 | errors) */ | |
217 | #endif /* STATISTICS */ | |
218 | }; | |
219 | ||
220 | /* ucc_slow_init | |
221 | * Initializes Slow UCC according to provided parameters. | |
222 | * | |
223 | * us_info - (In) pointer to the slow UCC info structure. | |
224 | * uccs_ret - (Out) pointer to the slow UCC structure. | |
225 | */ | |
226 | int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret); | |
227 | ||
228 | /* ucc_slow_free | |
229 | * Frees all resources for slow UCC. | |
230 | * | |
231 | * uccs - (In) pointer to the slow UCC structure. | |
232 | */ | |
233 | void ucc_slow_free(struct ucc_slow_private * uccs); | |
234 | ||
235 | /* ucc_slow_enable | |
236 | * Enables a fast UCC port. | |
237 | * This routine enables Tx and/or Rx through the General UCC Mode Register. | |
238 | * | |
239 | * uccs - (In) pointer to the slow UCC structure. | |
240 | * mode - (In) TX, RX, or both. | |
241 | */ | |
242 | void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode); | |
243 | ||
244 | /* ucc_slow_disable | |
245 | * Disables a fast UCC port. | |
246 | * This routine disables Tx and/or Rx through the General UCC Mode Register. | |
247 | * | |
248 | * uccs - (In) pointer to the slow UCC structure. | |
249 | * mode - (In) TX, RX, or both. | |
250 | */ | |
251 | void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode); | |
252 | ||
253 | /* ucc_slow_poll_transmitter_now | |
254 | * Immediately forces a poll of the transmitter for data to be sent. | |
255 | * Typically, the hardware performs a periodic poll for data that the | |
256 | * transmit routine has set up to be transmitted. In cases where | |
257 | * this polling cycle is not soon enough, this optional routine can | |
258 | * be invoked to force a poll right away, instead. Proper use for | |
259 | * each transmission for which this functionality is desired is to | |
260 | * call the transmit routine and then this routine right after. | |
261 | * | |
262 | * uccs - (In) pointer to the slow UCC structure. | |
263 | */ | |
264 | void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs); | |
265 | ||
266 | /* ucc_slow_graceful_stop_tx | |
267 | * Smoothly stops transmission on a specified slow UCC. | |
268 | * | |
269 | * uccs - (In) pointer to the slow UCC structure. | |
270 | */ | |
271 | void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs); | |
272 | ||
273 | /* ucc_slow_stop_tx | |
274 | * Stops transmission on a specified slow UCC. | |
275 | * | |
276 | * uccs - (In) pointer to the slow UCC structure. | |
277 | */ | |
278 | void ucc_slow_stop_tx(struct ucc_slow_private * uccs); | |
279 | ||
280 | /* ucc_slow_restart_x | |
281 | * Restarts transmitting on a specified slow UCC. | |
282 | * | |
283 | * uccs - (In) pointer to the slow UCC structure. | |
284 | */ | |
285 | void ucc_slow_restart_x(struct ucc_slow_private * uccs); | |
286 | ||
287 | u32 ucc_slow_get_qe_cr_subblock(int uccs_num); | |
288 | ||
289 | #endif /* __UCC_SLOW_H__ */ |