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1da177e4 LT |
1 | /* |
2 | * include/asm-ppc/m8260_pci.h | |
3 | * | |
4 | * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | #ifdef __KERNEL__ | |
13 | #ifndef __M8260_PCI_H | |
14 | #define __M8260_PCI_H | |
15 | ||
16 | #include <linux/pci_ids.h> | |
17 | ||
18 | /* | |
19 | * Define the vendor/device ID for the MPC8265. | |
20 | */ | |
21 | #define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA) | |
a6dbba77 | 22 | #define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA) |
1da177e4 LT |
23 | |
24 | #define M8265_PCIBR0 0x101ac | |
25 | #define M8265_PCIBR1 0x101b0 | |
26 | #define M8265_PCIMSK0 0x101c4 | |
27 | #define M8265_PCIMSK1 0x101c8 | |
28 | ||
29 | /* Bit definitions for PCIBR registers */ | |
30 | ||
31 | #define PCIBR_ENABLE 0x00000001 | |
32 | ||
33 | /* Bit definitions for PCIMSK registers */ | |
34 | ||
35 | #define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */ | |
36 | #define PCIMSK_64KiB 0xFFFF0000 | |
37 | #define PCIMSK_128KiB 0xFFFE0000 | |
38 | #define PCIMSK_256KiB 0xFFFC0000 | |
39 | #define PCIMSK_512KiB 0xFFF80000 | |
40 | #define PCIMSK_1MiB 0xFFF00000 | |
41 | #define PCIMSK_2MiB 0xFFE00000 | |
42 | #define PCIMSK_4MiB 0xFFC00000 | |
43 | #define PCIMSK_8MiB 0xFF800000 | |
44 | #define PCIMSK_16MiB 0xFF000000 | |
45 | #define PCIMSK_32MiB 0xFE000000 | |
46 | #define PCIMSK_64MiB 0xFC000000 | |
47 | #define PCIMSK_128MiB 0xF8000000 | |
48 | #define PCIMSK_256MiB 0xF0000000 | |
49 | #define PCIMSK_512MiB 0xE0000000 | |
50 | #define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */ | |
51 | ||
52 | ||
53 | #define M826X_SCCR_PCI_MODE_EN 0x100 | |
54 | ||
55 | ||
56 | /* | |
57 | * Outbound ATU registers (3 sets). These registers control how 60x bus (local) | |
58 | * addresses are translated to PCI addresses when the MPC826x is a PCI bus | |
59 | * master (initiator). | |
60 | */ | |
61 | ||
62 | #define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ | |
63 | #define POTAR_REG1 0x10818 | |
64 | #define POTAR_REG2 0x10830 | |
65 | ||
66 | #define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ | |
67 | #define POBAR_REG1 0x10820 | |
68 | #define POBAR_REG2 0x10838 | |
69 | ||
70 | #define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ | |
71 | #define POCMR_REG1 0x10828 | |
72 | #define POCMR_REG2 0x10840 | |
73 | ||
74 | /* Bit definitions for POMCR registers */ | |
75 | ||
76 | #define POCMR_MASK_4KiB 0x000FFFFF | |
77 | #define POCMR_MASK_8KiB 0x000FFFFE | |
78 | #define POCMR_MASK_16KiB 0x000FFFFC | |
79 | #define POCMR_MASK_32KiB 0x000FFFF8 | |
80 | #define POCMR_MASK_64KiB 0x000FFFF0 | |
81 | #define POCMR_MASK_128KiB 0x000FFFE0 | |
82 | #define POCMR_MASK_256KiB 0x000FFFC0 | |
83 | #define POCMR_MASK_512KiB 0x000FFF80 | |
84 | #define POCMR_MASK_1MiB 0x000FFF00 | |
85 | #define POCMR_MASK_2MiB 0x000FFE00 | |
86 | #define POCMR_MASK_4MiB 0x000FFC00 | |
87 | #define POCMR_MASK_8MiB 0x000FF800 | |
88 | #define POCMR_MASK_16MiB 0x000FF000 | |
89 | #define POCMR_MASK_32MiB 0x000FE000 | |
90 | #define POCMR_MASK_64MiB 0x000FC000 | |
91 | #define POCMR_MASK_128MiB 0x000F8000 | |
92 | #define POCMR_MASK_256MiB 0x000F0000 | |
93 | #define POCMR_MASK_512MiB 0x000E0000 | |
94 | #define POCMR_MASK_1GiB 0x000C0000 | |
95 | ||
96 | #define POCMR_ENABLE 0x80000000 | |
97 | #define POCMR_PCI_IO 0x40000000 | |
98 | #define POCMR_PREFETCH_EN 0x20000000 | |
99 | ||
100 | /* Soft PCI reset */ | |
101 | ||
102 | #define PCI_GCR_REG 0x10880 | |
103 | ||
104 | /* Bit definitions for PCI_GCR registers */ | |
105 | ||
106 | #define PCIGCR_PCI_BUS_EN 0x1 | |
107 | ||
108 | #define PCI_EMR_REG 0x10888 | |
109 | /* | |
110 | * Inbound ATU registers (2 sets). These registers control how PCI addresses | |
111 | * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. | |
112 | */ | |
113 | ||
114 | #define PITAR_REG1 0x108D0 | |
115 | #define PIBAR_REG1 0x108D8 | |
116 | #define PICMR_REG1 0x108E0 | |
117 | #define PITAR_REG0 0x108E8 | |
118 | #define PIBAR_REG0 0x108F0 | |
119 | #define PICMR_REG0 0x108F8 | |
120 | ||
121 | /* Bit definitions for PCI Inbound Comparison Mask registers */ | |
122 | ||
123 | #define PICMR_MASK_4KiB 0x000FFFFF | |
124 | #define PICMR_MASK_8KiB 0x000FFFFE | |
125 | #define PICMR_MASK_16KiB 0x000FFFFC | |
126 | #define PICMR_MASK_32KiB 0x000FFFF8 | |
127 | #define PICMR_MASK_64KiB 0x000FFFF0 | |
128 | #define PICMR_MASK_128KiB 0x000FFFE0 | |
129 | #define PICMR_MASK_256KiB 0x000FFFC0 | |
130 | #define PICMR_MASK_512KiB 0x000FFF80 | |
131 | #define PICMR_MASK_1MiB 0x000FFF00 | |
132 | #define PICMR_MASK_2MiB 0x000FFE00 | |
133 | #define PICMR_MASK_4MiB 0x000FFC00 | |
134 | #define PICMR_MASK_8MiB 0x000FF800 | |
135 | #define PICMR_MASK_16MiB 0x000FF000 | |
136 | #define PICMR_MASK_32MiB 0x000FE000 | |
137 | #define PICMR_MASK_64MiB 0x000FC000 | |
138 | #define PICMR_MASK_128MiB 0x000F8000 | |
139 | #define PICMR_MASK_256MiB 0x000F0000 | |
140 | #define PICMR_MASK_512MiB 0x000E0000 | |
141 | #define PICMR_MASK_1GiB 0x000C0000 | |
142 | ||
143 | #define PICMR_ENABLE 0x80000000 | |
144 | #define PICMR_NO_SNOOP_EN 0x40000000 | |
145 | #define PICMR_PREFETCH_EN 0x20000000 | |
146 | ||
147 | /* PCI error Registers */ | |
148 | ||
149 | #define PCI_ERROR_STATUS_REG 0x10884 | |
150 | #define PCI_ERROR_MASK_REG 0x10888 | |
151 | #define PCI_ERROR_CONTROL_REG 0x1088C | |
152 | #define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 | |
153 | #define PCI_ERROR_DATA_CAPTURE_REG 0x10898 | |
154 | #define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 | |
155 | ||
156 | /* PCI error Register bit defines */ | |
157 | ||
158 | #define PCI_ERROR_PCI_ADDR_PAR 0x00000001 | |
159 | #define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 | |
160 | #define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 | |
161 | #define PCI_ERROR_PCI_NO_RSP 0x00000008 | |
162 | #define PCI_ERROR_PCI_TAR_ABT 0x00000010 | |
163 | #define PCI_ERROR_PCI_SERR 0x00000020 | |
164 | #define PCI_ERROR_PCI_PERR_RD 0x00000040 | |
165 | #define PCI_ERROR_PCI_PERR_WR 0x00000080 | |
166 | #define PCI_ERROR_I2O_OFQO 0x00000100 | |
167 | #define PCI_ERROR_I2O_IPQO 0x00000200 | |
168 | #define PCI_ERROR_IRA 0x00000400 | |
169 | #define PCI_ERROR_NMI 0x00000800 | |
170 | #define PCI_ERROR_I2O_DBMC 0x00001000 | |
171 | ||
172 | /* | |
173 | * Register pair used to generate configuration cycles on the PCI bus | |
174 | * and access the MPC826x's own PCI configuration registers. | |
175 | */ | |
176 | ||
177 | #define PCI_CFG_ADDR_REG 0x10900 | |
178 | #define PCI_CFG_DATA_REG 0x10904 | |
179 | ||
180 | /* Bus parking decides where the bus control sits when idle */ | |
181 | /* If modifying memory controllers for PCI park on the core */ | |
182 | ||
183 | #define PPC_ACR_BUS_PARK_CORE 0x6 | |
184 | #define PPC_ACR_BUS_PARK_PCI 0x3 | |
185 | ||
186 | #endif /* __M8260_PCI_H */ | |
187 | #endif /* __KERNEL__ */ |