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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
3 | */ | |
4 | #ifndef __PPC_SYSTEM_H | |
5 | #define __PPC_SYSTEM_H | |
6 | ||
7 | #include <linux/config.h> | |
8 | #include <linux/kernel.h> | |
9 | ||
10 | #include <asm/atomic.h> | |
11 | #include <asm/hw_irq.h> | |
12 | ||
13 | /* | |
14 | * Memory barrier. | |
15 | * The sync instruction guarantees that all memory accesses initiated | |
16 | * by this processor have been performed (with respect to all other | |
17 | * mechanisms that access memory). The eieio instruction is a barrier | |
18 | * providing an ordering (separately) for (a) cacheable stores and (b) | |
19 | * loads and stores to non-cacheable memory (e.g. I/O devices). | |
20 | * | |
21 | * mb() prevents loads and stores being reordered across this point. | |
22 | * rmb() prevents loads being reordered across this point. | |
23 | * wmb() prevents stores being reordered across this point. | |
24 | * read_barrier_depends() prevents data-dependent loads being reordered | |
25 | * across this point (nop on PPC). | |
26 | * | |
27 | * We can use the eieio instruction for wmb, but since it doesn't | |
28 | * give any ordering guarantees about loads, we have to use the | |
29 | * stronger but slower sync instruction for mb and rmb. | |
30 | */ | |
31 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | |
32 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") | |
33 | #define wmb() __asm__ __volatile__ ("eieio" : : : "memory") | |
34 | #define read_barrier_depends() do { } while(0) | |
35 | ||
36 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
37 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | |
38 | ||
39 | #ifdef CONFIG_SMP | |
40 | #define smp_mb() mb() | |
41 | #define smp_rmb() rmb() | |
42 | #define smp_wmb() wmb() | |
43 | #define smp_read_barrier_depends() read_barrier_depends() | |
44 | #else | |
45 | #define smp_mb() barrier() | |
46 | #define smp_rmb() barrier() | |
47 | #define smp_wmb() barrier() | |
48 | #define smp_read_barrier_depends() do { } while(0) | |
49 | #endif /* CONFIG_SMP */ | |
50 | ||
51 | #ifdef __KERNEL__ | |
52 | struct task_struct; | |
53 | struct pt_regs; | |
54 | ||
55 | extern void print_backtrace(unsigned long *); | |
56 | extern void show_regs(struct pt_regs * regs); | |
57 | extern void flush_instruction_cache(void); | |
58 | extern void hard_reset_now(void); | |
59 | extern void poweroff_now(void); | |
60 | #ifdef CONFIG_6xx | |
61 | extern long _get_L2CR(void); | |
62 | extern long _get_L3CR(void); | |
63 | extern void _set_L2CR(unsigned long); | |
64 | extern void _set_L3CR(unsigned long); | |
65 | #else | |
66 | #define _get_L2CR() 0L | |
67 | #define _get_L3CR() 0L | |
68 | #define _set_L2CR(val) do { } while(0) | |
69 | #define _set_L3CR(val) do { } while(0) | |
70 | #endif | |
71 | extern void via_cuda_init(void); | |
72 | extern void pmac_nvram_init(void); | |
73 | extern void read_rtc_time(void); | |
74 | extern void pmac_find_display(void); | |
75 | extern void giveup_fpu(struct task_struct *); | |
76 | extern void enable_kernel_fp(void); | |
77 | extern void enable_kernel_altivec(void); | |
78 | extern void giveup_altivec(struct task_struct *); | |
79 | extern void load_up_altivec(struct task_struct *); | |
80 | extern void giveup_spe(struct task_struct *); | |
81 | extern void load_up_spe(struct task_struct *); | |
82 | extern int fix_alignment(struct pt_regs *); | |
83 | extern void cvt_fd(float *from, double *to, unsigned long *fpscr); | |
84 | extern void cvt_df(double *from, float *to, unsigned long *fpscr); | |
85 | extern int call_rtas(const char *, int, int, unsigned long *, ...); | |
86 | extern void cacheable_memzero(void *p, unsigned int nb); | |
e8834801 | 87 | extern void *cacheable_memcpy(void *, const void *, unsigned int); |
1da177e4 LT |
88 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); |
89 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | |
90 | extern void die(const char *, struct pt_regs *, long); | |
bb0bb3b6 | 91 | extern void _exception(int, struct pt_regs *, int, unsigned long); |
39cdc4bf KG |
92 | #ifdef CONFIG_BOOKE_WDT |
93 | extern u32 booke_wdt_enabled; | |
94 | extern u32 booke_wdt_period; | |
95 | #endif /* CONFIG_BOOKE_WDT */ | |
1da177e4 LT |
96 | |
97 | struct device_node; | |
98 | extern void note_scsi_host(struct device_node *, void *); | |
99 | ||
100 | extern struct task_struct *__switch_to(struct task_struct *, | |
101 | struct task_struct *); | |
102 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | |
103 | ||
104 | struct thread_struct; | |
105 | extern struct task_struct *_switch(struct thread_struct *prev, | |
106 | struct thread_struct *next); | |
107 | ||
108 | extern unsigned int rtas_data; | |
109 | ||
110 | static __inline__ unsigned long | |
111 | xchg_u32(volatile void *p, unsigned long val) | |
112 | { | |
113 | unsigned long prev; | |
114 | ||
115 | __asm__ __volatile__ ("\n\ | |
116 | 1: lwarx %0,0,%2 \n" | |
117 | PPC405_ERR77(0,%2) | |
118 | " stwcx. %3,0,%2 \n\ | |
119 | bne- 1b" | |
120 | : "=&r" (prev), "=m" (*(volatile unsigned long *)p) | |
121 | : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) | |
122 | : "cc", "memory"); | |
123 | ||
124 | return prev; | |
125 | } | |
126 | ||
127 | /* | |
128 | * This function doesn't exist, so you'll get a linker error | |
129 | * if something tries to do an invalid xchg(). | |
130 | */ | |
131 | extern void __xchg_called_with_bad_pointer(void); | |
132 | ||
133 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | |
134 | #define tas(ptr) (xchg((ptr),1)) | |
135 | ||
136 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) | |
137 | { | |
138 | switch (size) { | |
139 | case 4: | |
140 | return (unsigned long) xchg_u32(ptr, x); | |
141 | #if 0 /* xchg_u64 doesn't exist on 32-bit PPC */ | |
142 | case 8: | |
143 | return (unsigned long) xchg_u64(ptr, x); | |
144 | #endif /* 0 */ | |
145 | } | |
146 | __xchg_called_with_bad_pointer(); | |
147 | return x; | |
148 | ||
149 | ||
150 | } | |
151 | ||
152 | extern inline void * xchg_ptr(void * m, void * val) | |
153 | { | |
154 | return (void *) xchg_u32(m, (unsigned long) val); | |
155 | } | |
156 | ||
157 | ||
158 | #define __HAVE_ARCH_CMPXCHG 1 | |
159 | ||
160 | static __inline__ unsigned long | |
161 | __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) | |
162 | { | |
163 | unsigned int prev; | |
164 | ||
165 | __asm__ __volatile__ ("\n\ | |
166 | 1: lwarx %0,0,%2 \n\ | |
167 | cmpw 0,%0,%3 \n\ | |
168 | bne 2f \n" | |
169 | PPC405_ERR77(0,%2) | |
170 | " stwcx. %4,0,%2 \n\ | |
171 | bne- 1b\n" | |
172 | #ifdef CONFIG_SMP | |
173 | " sync\n" | |
174 | #endif /* CONFIG_SMP */ | |
175 | "2:" | |
176 | : "=&r" (prev), "=m" (*p) | |
177 | : "r" (p), "r" (old), "r" (new), "m" (*p) | |
178 | : "cc", "memory"); | |
179 | ||
180 | return prev; | |
181 | } | |
182 | ||
183 | /* This function doesn't exist, so you'll get a linker error | |
184 | if something tries to do an invalid cmpxchg(). */ | |
185 | extern void __cmpxchg_called_with_bad_pointer(void); | |
186 | ||
187 | static __inline__ unsigned long | |
188 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) | |
189 | { | |
190 | switch (size) { | |
191 | case 4: | |
192 | return __cmpxchg_u32(ptr, old, new); | |
193 | #if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */ | |
194 | case 8: | |
195 | return __cmpxchg_u64(ptr, old, new); | |
196 | #endif /* 0 */ | |
197 | } | |
198 | __cmpxchg_called_with_bad_pointer(); | |
199 | return old; | |
200 | } | |
201 | ||
202 | #define cmpxchg(ptr,o,n) \ | |
203 | ({ \ | |
204 | __typeof__(*(ptr)) _o_ = (o); \ | |
205 | __typeof__(*(ptr)) _n_ = (n); \ | |
206 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
207 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
208 | }) | |
209 | ||
210 | #define arch_align_stack(x) (x) | |
211 | ||
212 | #endif /* __KERNEL__ */ | |
213 | #endif /* __PPC_SYSTEM_H */ |