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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
3 | */ | |
4 | #ifndef __PPC_SYSTEM_H | |
5 | #define __PPC_SYSTEM_H | |
6 | ||
7 | #include <linux/config.h> | |
8 | #include <linux/kernel.h> | |
9 | ||
10 | #include <asm/atomic.h> | |
11 | #include <asm/hw_irq.h> | |
12 | ||
13 | /* | |
14 | * Memory barrier. | |
15 | * The sync instruction guarantees that all memory accesses initiated | |
16 | * by this processor have been performed (with respect to all other | |
17 | * mechanisms that access memory). The eieio instruction is a barrier | |
18 | * providing an ordering (separately) for (a) cacheable stores and (b) | |
19 | * loads and stores to non-cacheable memory (e.g. I/O devices). | |
20 | * | |
21 | * mb() prevents loads and stores being reordered across this point. | |
22 | * rmb() prevents loads being reordered across this point. | |
23 | * wmb() prevents stores being reordered across this point. | |
24 | * read_barrier_depends() prevents data-dependent loads being reordered | |
25 | * across this point (nop on PPC). | |
26 | * | |
27 | * We can use the eieio instruction for wmb, but since it doesn't | |
28 | * give any ordering guarantees about loads, we have to use the | |
29 | * stronger but slower sync instruction for mb and rmb. | |
30 | */ | |
31 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | |
32 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") | |
33 | #define wmb() __asm__ __volatile__ ("eieio" : : : "memory") | |
34 | #define read_barrier_depends() do { } while(0) | |
35 | ||
36 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
37 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | |
38 | ||
39 | #ifdef CONFIG_SMP | |
40 | #define smp_mb() mb() | |
41 | #define smp_rmb() rmb() | |
42 | #define smp_wmb() wmb() | |
43 | #define smp_read_barrier_depends() read_barrier_depends() | |
44 | #else | |
45 | #define smp_mb() barrier() | |
46 | #define smp_rmb() barrier() | |
47 | #define smp_wmb() barrier() | |
48 | #define smp_read_barrier_depends() do { } while(0) | |
49 | #endif /* CONFIG_SMP */ | |
50 | ||
51 | #ifdef __KERNEL__ | |
52 | struct task_struct; | |
53 | struct pt_regs; | |
54 | ||
55 | extern void print_backtrace(unsigned long *); | |
56 | extern void show_regs(struct pt_regs * regs); | |
57 | extern void flush_instruction_cache(void); | |
58 | extern void hard_reset_now(void); | |
59 | extern void poweroff_now(void); | |
60 | #ifdef CONFIG_6xx | |
61 | extern long _get_L2CR(void); | |
62 | extern long _get_L3CR(void); | |
63 | extern void _set_L2CR(unsigned long); | |
64 | extern void _set_L3CR(unsigned long); | |
65 | #else | |
66 | #define _get_L2CR() 0L | |
67 | #define _get_L3CR() 0L | |
68 | #define _set_L2CR(val) do { } while(0) | |
69 | #define _set_L3CR(val) do { } while(0) | |
70 | #endif | |
71 | extern void via_cuda_init(void); | |
72 | extern void pmac_nvram_init(void); | |
73 | extern void read_rtc_time(void); | |
74 | extern void pmac_find_display(void); | |
75 | extern void giveup_fpu(struct task_struct *); | |
76 | extern void enable_kernel_fp(void); | |
7ac59c62 | 77 | extern void flush_fp_to_thread(struct task_struct *); |
1da177e4 LT |
78 | extern void enable_kernel_altivec(void); |
79 | extern void giveup_altivec(struct task_struct *); | |
80 | extern void load_up_altivec(struct task_struct *); | |
fd582ec8 | 81 | extern int emulate_altivec(struct pt_regs *); |
1da177e4 LT |
82 | extern void giveup_spe(struct task_struct *); |
83 | extern void load_up_spe(struct task_struct *); | |
84 | extern int fix_alignment(struct pt_regs *); | |
85 | extern void cvt_fd(float *from, double *to, unsigned long *fpscr); | |
86 | extern void cvt_df(double *from, float *to, unsigned long *fpscr); | |
7ac59c62 PM |
87 | |
88 | #ifdef CONFIG_ALTIVEC | |
89 | extern void flush_altivec_to_thread(struct task_struct *); | |
90 | #else | |
91 | static inline void flush_altivec_to_thread(struct task_struct *t) | |
92 | { | |
93 | } | |
94 | #endif | |
95 | ||
96 | #ifdef CONFIG_SPE | |
97 | extern void flush_spe_to_thread(struct task_struct *); | |
98 | #else | |
99 | static inline void flush_spe_to_thread(struct task_struct *t) | |
100 | { | |
101 | } | |
102 | #endif | |
103 | ||
1da177e4 LT |
104 | extern int call_rtas(const char *, int, int, unsigned long *, ...); |
105 | extern void cacheable_memzero(void *p, unsigned int nb); | |
e8834801 | 106 | extern void *cacheable_memcpy(void *, const void *, unsigned int); |
1da177e4 LT |
107 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); |
108 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | |
dc1c1ca3 | 109 | extern int die(const char *, struct pt_regs *, long); |
bb0bb3b6 | 110 | extern void _exception(int, struct pt_regs *, int, unsigned long); |
fd582ec8 PM |
111 | void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); |
112 | ||
39cdc4bf KG |
113 | #ifdef CONFIG_BOOKE_WDT |
114 | extern u32 booke_wdt_enabled; | |
115 | extern u32 booke_wdt_period; | |
116 | #endif /* CONFIG_BOOKE_WDT */ | |
1da177e4 LT |
117 | |
118 | struct device_node; | |
119 | extern void note_scsi_host(struct device_node *, void *); | |
120 | ||
121 | extern struct task_struct *__switch_to(struct task_struct *, | |
122 | struct task_struct *); | |
123 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | |
124 | ||
125 | struct thread_struct; | |
126 | extern struct task_struct *_switch(struct thread_struct *prev, | |
127 | struct thread_struct *next); | |
128 | ||
129 | extern unsigned int rtas_data; | |
130 | ||
131 | static __inline__ unsigned long | |
132 | xchg_u32(volatile void *p, unsigned long val) | |
133 | { | |
134 | unsigned long prev; | |
135 | ||
136 | __asm__ __volatile__ ("\n\ | |
137 | 1: lwarx %0,0,%2 \n" | |
138 | PPC405_ERR77(0,%2) | |
139 | " stwcx. %3,0,%2 \n\ | |
140 | bne- 1b" | |
141 | : "=&r" (prev), "=m" (*(volatile unsigned long *)p) | |
142 | : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) | |
143 | : "cc", "memory"); | |
144 | ||
145 | return prev; | |
146 | } | |
147 | ||
148 | /* | |
149 | * This function doesn't exist, so you'll get a linker error | |
150 | * if something tries to do an invalid xchg(). | |
151 | */ | |
152 | extern void __xchg_called_with_bad_pointer(void); | |
153 | ||
154 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | |
155 | #define tas(ptr) (xchg((ptr),1)) | |
156 | ||
157 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) | |
158 | { | |
159 | switch (size) { | |
160 | case 4: | |
161 | return (unsigned long) xchg_u32(ptr, x); | |
162 | #if 0 /* xchg_u64 doesn't exist on 32-bit PPC */ | |
163 | case 8: | |
164 | return (unsigned long) xchg_u64(ptr, x); | |
165 | #endif /* 0 */ | |
166 | } | |
167 | __xchg_called_with_bad_pointer(); | |
168 | return x; | |
169 | ||
170 | ||
171 | } | |
172 | ||
173 | extern inline void * xchg_ptr(void * m, void * val) | |
174 | { | |
175 | return (void *) xchg_u32(m, (unsigned long) val); | |
176 | } | |
177 | ||
178 | ||
179 | #define __HAVE_ARCH_CMPXCHG 1 | |
180 | ||
181 | static __inline__ unsigned long | |
182 | __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) | |
183 | { | |
184 | unsigned int prev; | |
185 | ||
186 | __asm__ __volatile__ ("\n\ | |
187 | 1: lwarx %0,0,%2 \n\ | |
188 | cmpw 0,%0,%3 \n\ | |
189 | bne 2f \n" | |
190 | PPC405_ERR77(0,%2) | |
191 | " stwcx. %4,0,%2 \n\ | |
192 | bne- 1b\n" | |
193 | #ifdef CONFIG_SMP | |
194 | " sync\n" | |
195 | #endif /* CONFIG_SMP */ | |
196 | "2:" | |
197 | : "=&r" (prev), "=m" (*p) | |
198 | : "r" (p), "r" (old), "r" (new), "m" (*p) | |
199 | : "cc", "memory"); | |
200 | ||
201 | return prev; | |
202 | } | |
203 | ||
204 | /* This function doesn't exist, so you'll get a linker error | |
205 | if something tries to do an invalid cmpxchg(). */ | |
206 | extern void __cmpxchg_called_with_bad_pointer(void); | |
207 | ||
208 | static __inline__ unsigned long | |
209 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) | |
210 | { | |
211 | switch (size) { | |
212 | case 4: | |
213 | return __cmpxchg_u32(ptr, old, new); | |
214 | #if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */ | |
215 | case 8: | |
216 | return __cmpxchg_u64(ptr, old, new); | |
217 | #endif /* 0 */ | |
218 | } | |
219 | __cmpxchg_called_with_bad_pointer(); | |
220 | return old; | |
221 | } | |
222 | ||
223 | #define cmpxchg(ptr,o,n) \ | |
224 | ({ \ | |
225 | __typeof__(*(ptr)) _o_ = (o); \ | |
226 | __typeof__(*(ptr)) _n_ = (n); \ | |
227 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
228 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
229 | }) | |
230 | ||
231 | #define arch_align_stack(x) (x) | |
232 | ||
233 | #endif /* __KERNEL__ */ | |
234 | #endif /* __PPC_SYSTEM_H */ |