projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * include/asm-s390/sigp.h | |
| 3 | * | |
| 4 | * S390 version | |
| 5 | * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
| 6 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
| 7 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
| 8 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
| 9 | * | |
| 10 | * sigp.h by D.J. Barrow (c) IBM 1999 | |
| 11 | * contains routines / structures for signalling other S/390 processors in an | |
| 12 | * SMP configuration. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef __SIGP__ | |
| 16 | #define __SIGP__ | |
| 17 | ||
| 18 | #include <asm/ptrace.h> | |
| 19 | #include <asm/atomic.h> | |
| 20 | ||
| 21 | /* get real cpu address from logical cpu number */ | |
| 22 | extern volatile int __cpu_logical_map[]; | |
| 23 | ||
| 24 | typedef enum | |
| 25 | { | |
| 26 | sigp_unassigned=0x0, | |
| 27 | sigp_sense, | |
| 28 | sigp_external_call, | |
| 29 | sigp_emergency_signal, | |
| 30 | sigp_start, | |
| 31 | sigp_stop, | |
| 32 | sigp_restart, | |
| 33 | sigp_unassigned1, | |
| 34 | sigp_unassigned2, | |
| 35 | sigp_stop_and_store_status, | |
| 36 | sigp_unassigned3, | |
| 37 | sigp_initial_cpu_reset, | |
| 38 | sigp_cpu_reset, | |
| 39 | sigp_set_prefix, | |
| 40 | sigp_store_status_at_address, | |
| 41 | sigp_store_extended_status_at_address | |
| 42 | } sigp_order_code; | |
| 43 | ||
| 44 | typedef __u32 sigp_status_word; | |
| 45 | ||
| 46 | typedef enum | |
| 47 | { | |
| 48 | sigp_order_code_accepted=0, | |
| 49 | sigp_status_stored, | |
| 50 | sigp_busy, | |
| 51 | sigp_not_operational | |
| 52 | } sigp_ccode; | |
| 53 | ||
| 54 | ||
| 55 | /* | |
| 56 | * Definitions for the external call | |
| 57 | */ | |
| 58 | ||
| 59 | /* 'Bit' signals, asynchronous */ | |
| 60 | typedef enum | |
| 61 | { | |
| 62 | ec_schedule=0, | |
| 63 | ec_call_function, | |
| 64 | ec_bit_last | |
| 65 | } ec_bit_sig; | |
| 66 | ||
| 67 | /* | |
| 68 | * Signal processor | |
| 69 | */ | |
| 70 | extern __inline__ sigp_ccode | |
| 71 | signal_processor(__u16 cpu_addr, sigp_order_code order_code) | |
| 72 | { | |
| 73 | sigp_ccode ccode; | |
| 74 | ||
| 75 | __asm__ __volatile__( | |
| 76 | " sr 1,1\n" /* parameter=0 in gpr 1 */ | |
| 77 | " sigp 1,%1,0(%2)\n" | |
| 78 | " ipm %0\n" | |
| 79 | " srl %0,28\n" | |
| 80 | : "=d" (ccode) | |
| 81 | : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code) | |
| 82 | : "cc" , "memory", "1" ); | |
| 83 | return ccode; | |
| 84 | } | |
| 85 | ||
| 86 | /* | |
| 87 | * Signal processor with parameter | |
| 88 | */ | |
| 89 | extern __inline__ sigp_ccode | |
| 90 | signal_processor_p(__u32 parameter, __u16 cpu_addr, | |
| 91 | sigp_order_code order_code) | |
| 92 | { | |
| 93 | sigp_ccode ccode; | |
| 94 | ||
| 95 | __asm__ __volatile__( | |
| 96 | " lr 1,%1\n" /* parameter in gpr 1 */ | |
| 97 | " sigp 1,%2,0(%3)\n" | |
| 98 | " ipm %0\n" | |
| 99 | " srl %0,28\n" | |
| 100 | : "=d" (ccode) | |
| 101 | : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]), | |
| 102 | "a" (order_code) | |
| 103 | : "cc" , "memory", "1" ); | |
| 104 | return ccode; | |
| 105 | } | |
| 106 | ||
| 107 | /* | |
| 108 | * Signal processor with parameter and return status | |
| 109 | */ | |
| 110 | extern __inline__ sigp_ccode | |
| 111 | signal_processor_ps(__u32 *statusptr, __u32 parameter, | |
| 112 | __u16 cpu_addr, sigp_order_code order_code) | |
| 113 | { | |
| 114 | sigp_ccode ccode; | |
| 115 | ||
| 116 | __asm__ __volatile__( | |
| 117 | " sr 2,2\n" /* clear status */ | |
| 118 | " lr 3,%2\n" /* parameter in gpr 3 */ | |
| 119 | " sigp 2,%3,0(%4)\n" | |
| 120 | " st 2,%1\n" | |
| 121 | " ipm %0\n" | |
| 122 | " srl %0,28\n" | |
| 123 | : "=d" (ccode), "=m" (*statusptr) | |
| 124 | : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]), | |
| 125 | "a" (order_code) | |
| 126 | : "cc" , "memory", "2" , "3" | |
| 127 | ); | |
| 128 | return ccode; | |
| 129 | } | |
| 130 | ||
| 131 | #endif /* __SIGP__ */ |