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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/smp.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
7 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
8 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
9 | */ | |
10 | #ifndef __ASM_SMP_H | |
11 | #define __ASM_SMP_H | |
12 | ||
1da177e4 LT |
13 | #include <linux/threads.h> |
14 | #include <linux/cpumask.h> | |
15 | #include <linux/bitops.h> | |
16 | ||
17 | #if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__) | |
18 | ||
19 | #include <asm/lowcore.h> | |
20 | #include <asm/sigp.h> | |
21 | ||
22 | /* | |
23 | s390 specific smp.c headers | |
24 | */ | |
25 | typedef struct | |
26 | { | |
27 | int intresting; | |
28 | sigp_ccode ccode; | |
29 | __u32 status; | |
30 | __u16 cpu; | |
31 | } sigp_info; | |
32 | ||
255acee7 | 33 | extern void smp_setup_cpu_possible_map(void); |
1da177e4 LT |
34 | extern int smp_call_function_on(void (*func) (void *info), void *info, |
35 | int nonatomic, int wait, int cpu); | |
36 | #define NO_PROC_ID 0xFF /* No processor magic marker */ | |
37 | ||
38 | /* | |
39 | * This magic constant controls our willingness to transfer | |
40 | * a process across CPUs. Such a transfer incurs misses on the L1 | |
41 | * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My | |
42 | * gut feeling is this will vary by board in value. For a board | |
43 | * with separate L2 cache it probably depends also on the RSS, and | |
44 | * for a board with shared L2 cache it ought to decay fast as other | |
45 | * processes are run. | |
46 | */ | |
47 | ||
48 | #define PROC_CHANGE_PENALTY 20 /* Schedule penalty */ | |
49 | ||
39c715b7 | 50 | #define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr) |
1da177e4 LT |
51 | |
52 | extern int smp_get_cpu(cpumask_t cpu_map); | |
53 | extern void smp_put_cpu(int cpu); | |
54 | ||
4448aaf0 | 55 | static inline __u16 hard_smp_processor_id(void) |
1da177e4 LT |
56 | { |
57 | __u16 cpu_address; | |
58 | ||
94c12cc7 | 59 | asm volatile("stap %0" : "=m" (cpu_address)); |
1da177e4 LT |
60 | return cpu_address; |
61 | } | |
62 | ||
63 | /* | |
64 | * returns 1 if cpu is in stopped/check stopped state or not operational | |
65 | * returns 0 otherwise | |
66 | */ | |
67 | static inline int | |
68 | smp_cpu_not_running(int cpu) | |
69 | { | |
70 | __u32 status; | |
71 | ||
72 | switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) { | |
73 | case sigp_order_code_accepted: | |
74 | case sigp_status_stored: | |
75 | /* Check for stopped and check stop state */ | |
76 | if (status & 0x50) | |
77 | return 1; | |
78 | break; | |
79 | case sigp_not_operational: | |
80 | return 1; | |
81 | default: | |
82 | break; | |
83 | } | |
84 | return 0; | |
85 | } | |
86 | ||
87 | #define cpu_logical_map(cpu) (cpu) | |
88 | ||
89 | extern int __cpu_disable (void); | |
90 | extern void __cpu_die (unsigned int cpu); | |
91 | extern void cpu_die (void) __attribute__ ((noreturn)); | |
92 | extern int __cpu_up (unsigned int cpu); | |
93 | ||
94 | #endif | |
95 | ||
96 | #ifndef CONFIG_SMP | |
97 | static inline int | |
98 | smp_call_function_on(void (*func) (void *info), void *info, | |
99 | int nonatomic, int wait, int cpu) | |
100 | { | |
101 | func(info); | |
102 | return 0; | |
103 | } | |
a386fba2 | 104 | #define smp_cpu_not_running(cpu) 1 |
1da177e4 LT |
105 | #define smp_get_cpu(cpu) ({ 0; }) |
106 | #define smp_put_cpu(cpu) ({ 0; }) | |
39b083fe | 107 | #define smp_setup_cpu_possible_map() do { } while (0) |
1da177e4 LT |
108 | #endif |
109 | ||
110 | #endif |