Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/system.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), | |
7 | * | |
8 | * Derived from "include/asm-i386/system.h" | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_SYSTEM_H | |
12 | #define __ASM_SYSTEM_H | |
13 | ||
1da177e4 LT |
14 | #include <linux/kernel.h> |
15 | #include <asm/types.h> | |
16 | #include <asm/ptrace.h> | |
17 | #include <asm/setup.h> | |
77fa2245 | 18 | #include <asm/processor.h> |
1da177e4 LT |
19 | |
20 | #ifdef __KERNEL__ | |
21 | ||
22 | struct task_struct; | |
23 | ||
24 | extern struct task_struct *__switch_to(void *, void *); | |
25 | ||
1da177e4 LT |
26 | static inline void save_fp_regs(s390_fp_regs *fpregs) |
27 | { | |
94c12cc7 MS |
28 | asm volatile( |
29 | " std 0,8(%1)\n" | |
30 | " std 2,24(%1)\n" | |
31 | " std 4,40(%1)\n" | |
32 | " std 6,56(%1)" | |
33 | : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory"); | |
1da177e4 LT |
34 | if (!MACHINE_HAS_IEEE) |
35 | return; | |
36 | asm volatile( | |
94c12cc7 MS |
37 | " stfpc 0(%1)\n" |
38 | " std 1,16(%1)\n" | |
39 | " std 3,32(%1)\n" | |
40 | " std 5,48(%1)\n" | |
41 | " std 7,64(%1)\n" | |
42 | " std 8,72(%1)\n" | |
43 | " std 9,80(%1)\n" | |
44 | " std 10,88(%1)\n" | |
45 | " std 11,96(%1)\n" | |
46 | " std 12,104(%1)\n" | |
47 | " std 13,112(%1)\n" | |
48 | " std 14,120(%1)\n" | |
49 | " std 15,128(%1)\n" | |
50 | : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory"); | |
1da177e4 LT |
51 | } |
52 | ||
53 | static inline void restore_fp_regs(s390_fp_regs *fpregs) | |
54 | { | |
94c12cc7 MS |
55 | asm volatile( |
56 | " ld 0,8(%0)\n" | |
57 | " ld 2,24(%0)\n" | |
58 | " ld 4,40(%0)\n" | |
59 | " ld 6,56(%0)" | |
60 | : : "a" (fpregs), "m" (*fpregs)); | |
1da177e4 LT |
61 | if (!MACHINE_HAS_IEEE) |
62 | return; | |
63 | asm volatile( | |
94c12cc7 MS |
64 | " lfpc 0(%0)\n" |
65 | " ld 1,16(%0)\n" | |
66 | " ld 3,32(%0)\n" | |
67 | " ld 5,48(%0)\n" | |
68 | " ld 7,64(%0)\n" | |
69 | " ld 8,72(%0)\n" | |
70 | " ld 9,80(%0)\n" | |
71 | " ld 10,88(%0)\n" | |
72 | " ld 11,96(%0)\n" | |
73 | " ld 12,104(%0)\n" | |
74 | " ld 13,112(%0)\n" | |
75 | " ld 14,120(%0)\n" | |
76 | " ld 15,128(%0)\n" | |
77 | : : "a" (fpregs), "m" (*fpregs)); | |
1da177e4 LT |
78 | } |
79 | ||
80 | static inline void save_access_regs(unsigned int *acrs) | |
81 | { | |
94c12cc7 | 82 | asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory"); |
1da177e4 LT |
83 | } |
84 | ||
85 | static inline void restore_access_regs(unsigned int *acrs) | |
86 | { | |
94c12cc7 | 87 | asm volatile("lam 0,15,0(%0)" : : "a" (acrs)); |
1da177e4 LT |
88 | } |
89 | ||
90 | #define switch_to(prev,next,last) do { \ | |
91 | if (prev == next) \ | |
92 | break; \ | |
93 | save_fp_regs(&prev->thread.fp_regs); \ | |
94 | restore_fp_regs(&next->thread.fp_regs); \ | |
95 | save_access_regs(&prev->thread.acrs[0]); \ | |
96 | restore_access_regs(&next->thread.acrs[0]); \ | |
97 | prev = __switch_to(prev,next); \ | |
98 | } while (0) | |
99 | ||
1da177e4 | 100 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
1f1c12af MS |
101 | extern void account_vtime(struct task_struct *); |
102 | extern void account_tick_vtime(struct task_struct *); | |
1da177e4 | 103 | extern void account_system_vtime(struct task_struct *); |
5c833890 JB |
104 | #else |
105 | #define account_vtime(x) do { /* empty */ } while (0) | |
4866cde0 | 106 | #endif |
1da177e4 | 107 | |
29b08d2b HC |
108 | #ifdef CONFIG_PFAULT |
109 | extern void pfault_irq_init(void); | |
110 | extern int pfault_init(void); | |
111 | extern void pfault_fini(void); | |
112 | #else /* CONFIG_PFAULT */ | |
113 | #define pfault_irq_init() do { } while (0) | |
114 | #define pfault_init() ({-1;}) | |
115 | #define pfault_fini() do { } while (0) | |
116 | #endif /* CONFIG_PFAULT */ | |
117 | ||
5ee24d95 | 118 | #define finish_arch_switch(prev) do { \ |
1da177e4 | 119 | set_fs(current->thread.mm_segment); \ |
1f1c12af | 120 | account_vtime(prev); \ |
1da177e4 LT |
121 | } while (0) |
122 | ||
94c12cc7 | 123 | #define nop() asm volatile("nop") |
1da177e4 | 124 | |
5a651c93 HC |
125 | #define xchg(ptr,x) \ |
126 | ({ \ | |
127 | __typeof__(*(ptr)) __ret; \ | |
128 | __ret = (__typeof__(*(ptr))) \ | |
129 | __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \ | |
130 | __ret; \ | |
131 | }) | |
1da177e4 LT |
132 | |
133 | static inline unsigned long __xchg(unsigned long x, void * ptr, int size) | |
134 | { | |
135 | unsigned long addr, old; | |
136 | int shift; | |
137 | ||
138 | switch (size) { | |
139 | case 1: | |
140 | addr = (unsigned long) ptr; | |
141 | shift = (3 ^ (addr & 3)) << 3; | |
142 | addr ^= addr & 3; | |
143 | asm volatile( | |
94c12cc7 MS |
144 | " l %0,0(%4)\n" |
145 | "0: lr 0,%0\n" | |
146 | " nr 0,%3\n" | |
147 | " or 0,%2\n" | |
148 | " cs %0,0,0(%4)\n" | |
149 | " jl 0b\n" | |
1da177e4 LT |
150 | : "=&d" (old), "=m" (*(int *) addr) |
151 | : "d" (x << shift), "d" (~(255 << shift)), "a" (addr), | |
94c12cc7 | 152 | "m" (*(int *) addr) : "memory", "cc", "0"); |
1da177e4 LT |
153 | x = old >> shift; |
154 | break; | |
155 | case 2: | |
156 | addr = (unsigned long) ptr; | |
157 | shift = (2 ^ (addr & 2)) << 3; | |
158 | addr ^= addr & 2; | |
159 | asm volatile( | |
94c12cc7 MS |
160 | " l %0,0(%4)\n" |
161 | "0: lr 0,%0\n" | |
162 | " nr 0,%3\n" | |
163 | " or 0,%2\n" | |
164 | " cs %0,0,0(%4)\n" | |
165 | " jl 0b\n" | |
1da177e4 LT |
166 | : "=&d" (old), "=m" (*(int *) addr) |
167 | : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr), | |
94c12cc7 | 168 | "m" (*(int *) addr) : "memory", "cc", "0"); |
1da177e4 LT |
169 | x = old >> shift; |
170 | break; | |
171 | case 4: | |
94c12cc7 MS |
172 | asm volatile( |
173 | " l %0,0(%3)\n" | |
174 | "0: cs %0,%2,0(%3)\n" | |
175 | " jl 0b\n" | |
1da177e4 LT |
176 | : "=&d" (old), "=m" (*(int *) ptr) |
177 | : "d" (x), "a" (ptr), "m" (*(int *) ptr) | |
94c12cc7 | 178 | : "memory", "cc"); |
1da177e4 LT |
179 | x = old; |
180 | break; | |
181 | #ifdef __s390x__ | |
182 | case 8: | |
94c12cc7 MS |
183 | asm volatile( |
184 | " lg %0,0(%3)\n" | |
185 | "0: csg %0,%2,0(%3)\n" | |
186 | " jl 0b\n" | |
1da177e4 LT |
187 | : "=&d" (old), "=m" (*(long *) ptr) |
188 | : "d" (x), "a" (ptr), "m" (*(long *) ptr) | |
94c12cc7 | 189 | : "memory", "cc"); |
1da177e4 LT |
190 | x = old; |
191 | break; | |
192 | #endif /* __s390x__ */ | |
193 | } | |
194 | return x; | |
195 | } | |
196 | ||
197 | /* | |
198 | * Atomic compare and exchange. Compare OLD with MEM, if identical, | |
199 | * store NEW in MEM. Return the initial value in MEM. Success is | |
200 | * indicated by comparing RETURN with OLD. | |
201 | */ | |
202 | ||
203 | #define __HAVE_ARCH_CMPXCHG 1 | |
204 | ||
205 | #define cmpxchg(ptr,o,n)\ | |
206 | ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\ | |
207 | (unsigned long)(n),sizeof(*(ptr)))) | |
208 | ||
209 | static inline unsigned long | |
210 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) | |
211 | { | |
212 | unsigned long addr, prev, tmp; | |
213 | int shift; | |
214 | ||
215 | switch (size) { | |
216 | case 1: | |
217 | addr = (unsigned long) ptr; | |
218 | shift = (3 ^ (addr & 3)) << 3; | |
219 | addr ^= addr & 3; | |
220 | asm volatile( | |
94c12cc7 MS |
221 | " l %0,0(%4)\n" |
222 | "0: nr %0,%5\n" | |
223 | " lr %1,%0\n" | |
224 | " or %0,%2\n" | |
225 | " or %1,%3\n" | |
226 | " cs %0,%1,0(%4)\n" | |
227 | " jnl 1f\n" | |
228 | " xr %1,%0\n" | |
229 | " nr %1,%5\n" | |
230 | " jnz 0b\n" | |
1da177e4 LT |
231 | "1:" |
232 | : "=&d" (prev), "=&d" (tmp) | |
233 | : "d" (old << shift), "d" (new << shift), "a" (ptr), | |
234 | "d" (~(255 << shift)) | |
94c12cc7 | 235 | : "memory", "cc"); |
1da177e4 LT |
236 | return prev >> shift; |
237 | case 2: | |
238 | addr = (unsigned long) ptr; | |
239 | shift = (2 ^ (addr & 2)) << 3; | |
240 | addr ^= addr & 2; | |
241 | asm volatile( | |
94c12cc7 MS |
242 | " l %0,0(%4)\n" |
243 | "0: nr %0,%5\n" | |
244 | " lr %1,%0\n" | |
245 | " or %0,%2\n" | |
246 | " or %1,%3\n" | |
247 | " cs %0,%1,0(%4)\n" | |
248 | " jnl 1f\n" | |
249 | " xr %1,%0\n" | |
250 | " nr %1,%5\n" | |
251 | " jnz 0b\n" | |
1da177e4 LT |
252 | "1:" |
253 | : "=&d" (prev), "=&d" (tmp) | |
254 | : "d" (old << shift), "d" (new << shift), "a" (ptr), | |
255 | "d" (~(65535 << shift)) | |
94c12cc7 | 256 | : "memory", "cc"); |
1da177e4 LT |
257 | return prev >> shift; |
258 | case 4: | |
94c12cc7 MS |
259 | asm volatile( |
260 | " cs %0,%2,0(%3)\n" | |
1da177e4 | 261 | : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr) |
94c12cc7 | 262 | : "memory", "cc"); |
1da177e4 LT |
263 | return prev; |
264 | #ifdef __s390x__ | |
265 | case 8: | |
94c12cc7 MS |
266 | asm volatile( |
267 | " csg %0,%2,0(%3)\n" | |
1da177e4 | 268 | : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr) |
94c12cc7 | 269 | : "memory", "cc"); |
1da177e4 LT |
270 | return prev; |
271 | #endif /* __s390x__ */ | |
272 | } | |
273 | return old; | |
274 | } | |
275 | ||
276 | /* | |
277 | * Force strict CPU ordering. | |
278 | * And yes, this is required on UP too when we're talking | |
279 | * to devices. | |
280 | * | |
281 | * This is very similar to the ppc eieio/sync instruction in that is | |
282 | * does a checkpoint syncronisation & makes sure that | |
283 | * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ). | |
284 | */ | |
285 | ||
94c12cc7 MS |
286 | #define eieio() asm volatile("bcr 15,0" : : : "memory") |
287 | #define SYNC_OTHER_CORES(x) eieio() | |
1da177e4 LT |
288 | #define mb() eieio() |
289 | #define rmb() eieio() | |
290 | #define wmb() eieio() | |
291 | #define read_barrier_depends() do { } while(0) | |
292 | #define smp_mb() mb() | |
293 | #define smp_rmb() rmb() | |
294 | #define smp_wmb() wmb() | |
295 | #define smp_read_barrier_depends() read_barrier_depends() | |
296 | #define smp_mb__before_clear_bit() smp_mb() | |
297 | #define smp_mb__after_clear_bit() smp_mb() | |
298 | ||
299 | ||
300 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
1da177e4 | 301 | |
1da177e4 LT |
302 | #ifdef __s390x__ |
303 | ||
94c12cc7 MS |
304 | #define __ctl_load(array, low, high) ({ \ |
305 | typedef struct { char _[sizeof(array)]; } addrtype; \ | |
306 | asm volatile( \ | |
307 | " lctlg %1,%2,0(%0)\n" \ | |
308 | : : "a" (&array), "i" (low), "i" (high), \ | |
309 | "m" (*(addrtype *)(array))); \ | |
1da177e4 LT |
310 | }) |
311 | ||
94c12cc7 MS |
312 | #define __ctl_store(array, low, high) ({ \ |
313 | typedef struct { char _[sizeof(array)]; } addrtype; \ | |
314 | asm volatile( \ | |
315 | " stctg %2,%3,0(%1)\n" \ | |
316 | : "=m" (*(addrtype *)(array)) \ | |
317 | : "a" (&array), "i" (low), "i" (high)); \ | |
1da177e4 LT |
318 | }) |
319 | ||
1da177e4 LT |
320 | #else /* __s390x__ */ |
321 | ||
94c12cc7 MS |
322 | #define __ctl_load(array, low, high) ({ \ |
323 | typedef struct { char _[sizeof(array)]; } addrtype; \ | |
324 | asm volatile( \ | |
325 | " lctl %1,%2,0(%0)\n" \ | |
326 | : : "a" (&array), "i" (low), "i" (high), \ | |
327 | "m" (*(addrtype *)(array))); \ | |
328 | }) | |
1da177e4 | 329 | |
94c12cc7 MS |
330 | #define __ctl_store(array, low, high) ({ \ |
331 | typedef struct { char _[sizeof(array)]; } addrtype; \ | |
332 | asm volatile( \ | |
333 | " stctl %2,%3,0(%1)\n" \ | |
334 | : "=m" (*(addrtype *)(array)) \ | |
335 | : "a" (&array), "i" (low), "i" (high)); \ | |
1da177e4 LT |
336 | }) |
337 | ||
1da177e4 LT |
338 | #endif /* __s390x__ */ |
339 | ||
94c12cc7 MS |
340 | #define __ctl_set_bit(cr, bit) ({ \ |
341 | unsigned long __dummy; \ | |
342 | __ctl_store(__dummy, cr, cr); \ | |
343 | __dummy |= 1UL << (bit); \ | |
344 | __ctl_load(__dummy, cr, cr); \ | |
345 | }) | |
346 | ||
347 | #define __ctl_clear_bit(cr, bit) ({ \ | |
348 | unsigned long __dummy; \ | |
349 | __ctl_store(__dummy, cr, cr); \ | |
350 | __dummy &= ~(1UL << (bit)); \ | |
351 | __ctl_load(__dummy, cr, cr); \ | |
352 | }) | |
353 | ||
1f194a4c | 354 | #include <linux/irqflags.h> |
1da177e4 | 355 | |
77fa2245 HC |
356 | /* |
357 | * Use to set psw mask except for the first byte which | |
358 | * won't be changed by this function. | |
359 | */ | |
360 | static inline void | |
361 | __set_psw_mask(unsigned long mask) | |
362 | { | |
94c12cc7 | 363 | __load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8))); |
77fa2245 HC |
364 | } |
365 | ||
c1821c2e GS |
366 | #define local_mcck_enable() __set_psw_mask(psw_kernel_bits) |
367 | #define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK) | |
77fa2245 | 368 | |
1da177e4 LT |
369 | #ifdef CONFIG_SMP |
370 | ||
371 | extern void smp_ctl_set_bit(int cr, int bit); | |
372 | extern void smp_ctl_clear_bit(int cr, int bit); | |
373 | #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit) | |
374 | #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit) | |
375 | ||
376 | #else | |
377 | ||
378 | #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit) | |
379 | #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit) | |
380 | ||
381 | #endif /* CONFIG_SMP */ | |
382 | ||
383 | extern void (*_machine_restart)(char *command); | |
384 | extern void (*_machine_halt)(void); | |
385 | extern void (*_machine_power_off)(void); | |
386 | ||
387 | #define arch_align_stack(x) (x) | |
388 | ||
389 | #endif /* __KERNEL__ */ | |
390 | ||
391 | #endif |