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1da177e4 LT |
1 | /* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $ |
2 | * | |
3 | * include/asm-sh/cache.h | |
4 | * | |
5 | * Copyright 1999 (C) Niibe Yutaka | |
6 | * Copyright 2002, 2003 (C) Paul Mundt | |
7 | */ | |
8 | #ifndef __ASM_SH_CACHE_H | |
9 | #define __ASM_SH_CACHE_H | |
10 | #ifdef __KERNEL__ | |
11 | ||
357d5946 | 12 | #include <linux/init.h> |
1da177e4 | 13 | #include <asm/cpu/cache.h> |
1da177e4 LT |
14 | |
15 | #define SH_CACHE_VALID 1 | |
16 | #define SH_CACHE_UPDATED 2 | |
17 | #define SH_CACHE_COMBINED 4 | |
18 | #define SH_CACHE_ASSOC 8 | |
19 | ||
20 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | |
21 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | |
22 | ||
23 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) | |
24 | ||
87e29cac | 25 | #ifndef __ASSEMBLY__ |
1da177e4 | 26 | struct cache_info { |
b638d0b9 RC |
27 | unsigned int ways; /* Number of cache ways */ |
28 | unsigned int sets; /* Number of cache sets */ | |
29 | unsigned int linesz; /* Cache line size (bytes) */ | |
1da177e4 | 30 | |
b638d0b9 | 31 | unsigned int way_size; /* sets * line size */ |
1da177e4 | 32 | |
b638d0b9 RC |
33 | /* |
34 | * way_incr is the address offset for accessing the next way | |
35 | * in memory mapped cache array ops. | |
36 | */ | |
37 | unsigned int way_incr; | |
1da177e4 LT |
38 | unsigned int entry_shift; |
39 | unsigned int entry_mask; | |
40 | ||
b638d0b9 RC |
41 | /* |
42 | * Compute a mask which selects the address bits which overlap between | |
43 | * 1. those used to select the cache set during indexing | |
44 | * 2. those in the physical page number. | |
45 | */ | |
46 | unsigned int alias_mask; | |
47 | ||
48 | unsigned int n_aliases; /* Number of aliases */ | |
49 | ||
1da177e4 LT |
50 | unsigned long flags; |
51 | }; | |
357d5946 PM |
52 | |
53 | int __init detect_cpu_and_cache_system(void); | |
54 | ||
87e29cac | 55 | #endif /* __ASSEMBLY__ */ |
1da177e4 LT |
56 | #endif /* __KERNEL__ */ |
57 | #endif /* __ASM_SH_CACHE_H */ |