[deliverable/linux.git] / include / asm-sh / dma.h

/*
 * include/asm-sh/dma.h
 *
 * Copyright (C) 2003, 2004  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#ifndef __ASM_SH_DMA_H
#define __ASM_SH_DMA_H
#ifdef __KERNEL__

#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/sysdev.h>
#include <asm/cpu/dma.h>

/* The maximum address that we can perform a DMA transfer to on this platform */
/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
   occurrence should be flagged as an error.  */
/* But... */
/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
#define MAX_DMA_ADDRESS		(PAGE_OFFSET+0x10000000)

#ifdef CONFIG_NR_DMA_CHANNELS
#  define MAX_DMA_CHANNELS	(CONFIG_NR_DMA_CHANNELS)
#else
#  define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
#endif

/*
 * Read and write modes can mean drastically different things depending on the
 * channel configuration. Consult your DMAC documentation and module
 * implementation for further clues.
 */
#define DMA_MODE_READ		0x00
#define DMA_MODE_WRITE		0x01
#define DMA_MODE_MASK		0x01

#define DMA_AUTOINIT		0x10

/*
 * DMAC (dma_info) flags
 */
enum {
	DMAC_CHANNELS_CONFIGURED	= 0x01,
	DMAC_CHANNELS_TEI_CAPABLE	= 0x02,	/* Transfer end interrupt */
};

/*
 * DMA channel capabilities / flags
 */
enum {
	DMA_CONFIGURED			= 0x01,

	/*
	 * Transfer end interrupt, inherited from DMAC.
	 * wait_queue used in dma_wait_for_completion.
	 */
	DMA_TEI_CAPABLE			= 0x02,
};

extern spinlock_t dma_spin_lock;

struct dma_channel;

struct dma_ops {
	int (*request)(struct dma_channel *chan);
	void (*free)(struct dma_channel *chan);

	int (*get_residue)(struct dma_channel *chan);
	int (*xfer)(struct dma_channel *chan);
	int (*configure)(struct dma_channel *chan, unsigned long flags);
	int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
};

struct dma_channel {
	char dev_id[16];		/* unique name per DMAC of channel */

	unsigned int chan;		/* DMAC channel number */
	unsigned int vchan;		/* Virtual channel number */

	unsigned int mode;
	unsigned int count;

	unsigned long sar;
	unsigned long dar;

	const char **caps;

	unsigned long flags;
	atomic_t busy;

	wait_queue_head_t wait_queue;

	struct sys_device dev;
	void *priv_data;
};

struct dma_info {
	struct platform_device *pdev;

	const char *name;
	unsigned int nr_channels;
	unsigned long flags;

	struct dma_ops *ops;
	struct dma_channel *channels;

	struct list_head list;
	int first_channel_nr;
};

struct dma_chan_caps {
	int ch_num;
	const char **caplist;
};

#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)

/* arch/sh/drivers/dma/dma-api.c */
extern int dma_xfer(unsigned int chan, unsigned long from,
		    unsigned long to, size_t size, unsigned int mode);

#define dma_write(chan, from, to, size)	\
	dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
#define dma_write_page(chan, from, to)	\
	dma_write(chan, from, to, PAGE_SIZE)

#define dma_read(chan, from, to, size)	\
	dma_xfer(chan, from, to, size, DMA_MODE_READ)
#define dma_read_page(chan, from, to)	\
	dma_read(chan, from, to, PAGE_SIZE)

extern int request_dma_bycap(const char **dmac, const char **caps,
			     const char *dev_id);
extern int request_dma(unsigned int chan, const char *dev_id);
extern void free_dma(unsigned int chan);
extern int get_dma_residue(unsigned int chan);
extern struct dma_info *get_dma_info(unsigned int chan);
extern struct dma_channel *get_dma_channel(unsigned int chan);
extern void dma_wait_for_completion(unsigned int chan);
extern void dma_configure_channel(unsigned int chan, unsigned long flags);

extern int register_dmac(struct dma_info *info);
extern void unregister_dmac(struct dma_info *info);
extern struct dma_info *get_dma_info_by_name(const char *dmac_name);

extern int dma_extend(unsigned int chan, unsigned long op, void *param);
extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);

#ifdef CONFIG_SYSFS
/* arch/sh/drivers/dma/dma-sysfs.c */
extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
#else
#define dma_create_sysfs_file(channel, info)		do { } while (0)
#define dma_remove_sysfs_file(channel, info)		do { } while (0)
#endif

#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy	(0)
#endif

#endif /* __KERNEL__ */
#endif /* __ASM_SH_DMA_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-sh/dma.h
	3	*
	4	* Copyright (C) 2003, 2004 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#ifndef __ASM_SH_DMA_H
	11	#define __ASM_SH_DMA_H
	12	#ifdef __KERNEL__
	13
1da177e4 LT	14	#include <linux/spinlock.h>
1da177e4 LT	15	#include <linux/wait.h>
66c5227e	16	#include <linux/sched.h>
1da177e4 LT	17	#include <linux/sysdev.h>
1da177e4 LT	18	#include <asm/cpu/dma.h>
1da177e4 LT	19
	20	/* The maximum address that we can perform a DMA transfer to on this platform */
	21	/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
	22	occurrence should be flagged as an error. */
	23	/* But... */
	24	/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
	25	#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
	26
	27	#ifdef CONFIG_NR_DMA_CHANNELS
	28	# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
	29	#else
	30	# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
	31	#endif
	32
	33	/*
	34	* Read and write modes can mean drastically different things depending on the
	35	* channel configuration. Consult your DMAC documentation and module
	36	* implementation for further clues.
	37	*/
	38	#define DMA_MODE_READ 0x00
	39	#define DMA_MODE_WRITE 0x01
	40	#define DMA_MODE_MASK 0x01
	41
	42	#define DMA_AUTOINIT 0x10
	43
	44	/*
	45	* DMAC (dma_info) flags
	46	*/
	47	enum {
db9b99d4 MG	48	DMAC_CHANNELS_CONFIGURED = 0x01,
db9b99d4 MG	49	DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */
1da177e4 LT	50	};
	51
	52	/*
	53	* DMA channel capabilities / flags
	54	*/
	55	enum {
db9b99d4 MG	56	DMA_CONFIGURED = 0x01,
	57
	58	/*
	59	* Transfer end interrupt, inherited from DMAC.
	60	* wait_queue used in dma_wait_for_completion.
	61	*/
	62	DMA_TEI_CAPABLE = 0x02,
1da177e4 LT	63	};
	64
	65	extern spinlock_t dma_spin_lock;
	66
	67	struct dma_channel;
	68
	69	struct dma_ops {
	70	int (request)(struct dma_channel chan);
	71	void (free)(struct dma_channel chan);
	72
	73	int (get_residue)(struct dma_channel chan);
	74	int (xfer)(struct dma_channel chan);
db9b99d4 MG	75	int (configure)(struct dma_channel chan, unsigned long flags);
db9b99d4 MG	76	int (extend)(struct dma_channel chan, unsigned long op, void *param);
1da177e4 LT	77	};
	78
	79	struct dma_channel {
db9b99d4	80	char dev_id[16]; /* unique name per DMAC of channel */
1da177e4	81
db9b99d4	82	unsigned int chan; /* DMAC channel number */
0d831770	83	unsigned int vchan; /* Virtual channel number */
db9b99d4	84
1da177e4 LT	85	unsigned int mode;
	86	unsigned int count;
	87
	88	unsigned long sar;
	89	unsigned long dar;
	90
db9b99d4 MG	91	const char **caps;
db9b99d4 MG	92
1da177e4 LT	93	unsigned long flags;
	94	atomic_t busy;
	95
1da177e4 LT	96	wait_queue_head_t wait_queue;
	97
	98	struct sys_device dev;
db9b99d4	99	void *priv_data;
1da177e4 LT	100	};
	101
	102	struct dma_info {
0d831770 PM	103	struct platform_device *pdev;
0d831770 PM	104
1da177e4 LT	105	const char *name;
	106	unsigned int nr_channels;
	107	unsigned long flags;
	108
	109	struct dma_ops *ops;
	110	struct dma_channel *channels;
	111
	112	struct list_head list;
db9b99d4 MG	113	int first_channel_nr;
	114	};
	115
	116	struct dma_chan_caps {
	117	int ch_num;
	118	const char **caplist;
1da177e4 LT	119	};
	120
	121	#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
	122
	123	/* arch/sh/drivers/dma/dma-api.c */
	124	extern int dma_xfer(unsigned int chan, unsigned long from,
	125	unsigned long to, size_t size, unsigned int mode);
	126
	127	#define dma_write(chan, from, to, size) \
	128	dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
	129	#define dma_write_page(chan, from, to) \
	130	dma_write(chan, from, to, PAGE_SIZE)
	131
	132	#define dma_read(chan, from, to, size) \
	133	dma_xfer(chan, from, to, size, DMA_MODE_READ)
	134	#define dma_read_page(chan, from, to) \
	135	dma_read(chan, from, to, PAGE_SIZE)
	136
db9b99d4 MG	137	extern int request_dma_bycap(const char dmac, const char caps,
db9b99d4 MG	138	const char *dev_id);
1da177e4 LT	139	extern int request_dma(unsigned int chan, const char *dev_id);
	140	extern void free_dma(unsigned int chan);
	141	extern int get_dma_residue(unsigned int chan);
	142	extern struct dma_info *get_dma_info(unsigned int chan);
	143	extern struct dma_channel *get_dma_channel(unsigned int chan);
	144	extern void dma_wait_for_completion(unsigned int chan);
	145	extern void dma_configure_channel(unsigned int chan, unsigned long flags);
	146
	147	extern int register_dmac(struct dma_info *info);
	148	extern void unregister_dmac(struct dma_info *info);
db9b99d4 MG	149	extern struct dma_info get_dma_info_by_name(const char dmac_name);
	150
	151	extern int dma_extend(unsigned int chan, unsigned long op, void *param);
	152	extern int register_chan_caps(const char dmac, struct dma_chan_caps capslist);
1da177e4 LT	153
	154	#ifdef CONFIG_SYSFS
	155	/* arch/sh/drivers/dma/dma-sysfs.c */
0d831770 PM	156	extern int dma_create_sysfs_files(struct dma_channel , struct dma_info );
	157	extern void dma_remove_sysfs_files(struct dma_channel , struct dma_info );
	158	#else
	159	#define dma_create_sysfs_file(channel, info) do { } while (0)
	160	#define dma_remove_sysfs_file(channel, info) do { } while (0)
1da177e4 LT	161	#endif
	162
	163	#ifdef CONFIG_PCI
	164	extern int isa_dma_bridge_buggy;
	165	#else
	166	#define isa_dma_bridge_buggy (0)
	167	#endif
	168
	169	#endif /* __KERNEL__ */
	170	#endif /* __ASM_SH_DMA_H */