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1da177e4 LT |
1 | #ifndef __ASM_SH_HD64461 |
2 | #define __ASM_SH_HD64461 | |
3 | /* | |
4 | * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $ | |
5 | * Copyright (C) 2000 YAEGASHI Takeshi | |
6 | * Hitachi HD64461 companion chip support | |
7 | */ | |
1da177e4 LT |
8 | |
9 | /* Constants for PCMCIA mappings */ | |
10 | #define HD64461_PCC_WINDOW 0x01000000 | |
11 | ||
12 | #define HD64461_PCC0_BASE 0xb8000000 /* area 6 */ | |
13 | #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) | |
14 | #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) | |
15 | #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) | |
16 | ||
17 | #define HD64461_PCC1_BASE 0xb4000000 /* area 5 */ | |
18 | #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) | |
19 | #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) | |
20 | ||
21 | #define HD64461_STBCR 0x10000 | |
22 | #define HD64461_STBCR_CKIO_STBY 0x2000 | |
23 | #define HD64461_STBCR_SAFECKE_IST 0x1000 | |
24 | #define HD64461_STBCR_SLCKE_IST 0x0800 | |
25 | #define HD64461_STBCR_SAFECKE_OST 0x0400 | |
26 | #define HD64461_STBCR_SLCKE_OST 0x0200 | |
27 | #define HD64461_STBCR_SMIAST 0x0100 | |
28 | #define HD64461_STBCR_SLCDST 0x0080 | |
29 | #define HD64461_STBCR_SPC0ST 0x0040 | |
30 | #define HD64461_STBCR_SPC1ST 0x0020 | |
31 | #define HD64461_STBCR_SAFEST 0x0010 | |
32 | #define HD64461_STBCR_STM0ST 0x0008 | |
33 | #define HD64461_STBCR_STM1ST 0x0004 | |
34 | #define HD64461_STBCR_SIRST 0x0002 | |
35 | #define HD64461_STBCR_SURTST 0x0001 | |
36 | ||
37 | #define HD64461_SYSCR 0x10002 | |
38 | #define HD64461_SCPUCR 0x10004 | |
39 | ||
40 | #define HD64461_LCDCBAR 0x11000 | |
41 | #define HD64461_LCDCLOR 0x11002 | |
42 | #define HD64461_LCDCCR 0x11004 | |
3aa770e7 AS |
43 | #define HD64461_LCDCCR_STBACK 0x0400 |
44 | #define HD64461_LCDCCR_STREQ 0x0100 | |
45 | #define HD64461_LCDCCR_MOFF 0x0080 | |
46 | #define HD64461_LCDCCR_REFSEL 0x0040 | |
47 | #define HD64461_LCDCCR_EPON 0x0020 | |
48 | #define HD64461_LCDCCR_SPON 0x0010 | |
1da177e4 LT |
49 | |
50 | #define HD64461_LDR1 0x11010 | |
51 | #define HD64461_LDR1_DON 0x01 | |
52 | #define HD64461_LDR1_DINV 0x80 | |
53 | ||
54 | #define HD64461_LDR2 0x11012 | |
55 | #define HD64461_LDHNCR 0x11014 | |
56 | #define HD64461_LDHNSR 0x11016 | |
57 | #define HD64461_LDVNTR 0x11018 | |
58 | #define HD64461_LDVNDR 0x1101a | |
59 | #define HD64461_LDVSPR 0x1101c | |
60 | #define HD64461_LDR3 0x1101e | |
61 | ||
6d75e650 | 62 | #define HD64461_CPTWAR 0x11030 |
1da177e4 | 63 | #define HD64461_CPTWDR 0x11032 |
6d75e650 | 64 | #define HD64461_CPTRAR 0x11034 |
1da177e4 LT |
65 | #define HD64461_CPTRDR 0x11036 |
66 | ||
67 | #define HD64461_GRDOR 0x11040 | |
68 | #define HD64461_GRSCR 0x11042 | |
69 | #define HD64461_GRCFGR 0x11044 | |
70 | #define HD64461_GRCFGR_ACCSTATUS 0x10 | |
71 | #define HD64461_GRCFGR_ACCRESET 0x08 | |
72 | #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 | |
73 | #define HD64461_GRCFGR_ACCSTART_LINE 0x04 | |
74 | #define HD64461_GRCFGR_COLORDEPTH16 0x01 | |
75 | ||
76 | #define HD64461_LNSARH 0x11046 | |
77 | #define HD64461_LNSARL 0x11048 | |
78 | #define HD64461_LNAXLR 0x1104a | |
79 | #define HD64461_LNDGR 0x1104c | |
80 | #define HD64461_LNAXR 0x1104e | |
81 | #define HD64461_LNERTR 0x11050 | |
82 | #define HD64461_LNMDR 0x11052 | |
83 | #define HD64461_BBTSSARH 0x11054 | |
84 | #define HD64461_BBTSSARL 0x11056 | |
85 | #define HD64461_BBTDSARH 0x11058 | |
86 | #define HD64461_BBTDSARL 0x1105a | |
87 | #define HD64461_BBTDWR 0x1105c | |
88 | #define HD64461_BBTDHR 0x1105e | |
89 | #define HD64461_BBTPARH 0x11060 | |
90 | #define HD64461_BBTPARL 0x11062 | |
91 | #define HD64461_BBTMARH 0x11064 | |
92 | #define HD64461_BBTMARL 0x11066 | |
93 | #define HD64461_BBTROPR 0x11068 | |
94 | #define HD64461_BBTMDR 0x1106a | |
95 | ||
96 | /* PC Card Controller Registers */ | |
97 | #define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ | |
98 | #define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ | |
99 | #define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ | |
100 | #define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ | |
101 | #define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ | |
102 | #define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ | |
103 | #define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ | |
104 | #define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ | |
105 | #define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ | |
106 | #define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ | |
107 | ||
108 | /* PCC Interface Status Register */ | |
109 | #define HD64461_PCCISR_READY 0x80 /* card ready */ | |
110 | #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ | |
111 | #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ | |
112 | #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ | |
113 | #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ | |
114 | #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ | |
115 | #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ | |
116 | #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ | |
117 | ||
118 | #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ | |
6d75e650 | 119 | #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ |
1da177e4 LT |
120 | #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ |
121 | #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ | |
122 | #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ | |
123 | #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ | |
124 | ||
125 | /* PCC General Control Register */ | |
126 | #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ | |
127 | #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ | |
128 | #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ | |
129 | #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ | |
130 | #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ | |
131 | #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ | |
132 | #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ | |
133 | #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ | |
134 | ||
135 | /* PCC Card Status Change Register */ | |
136 | #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ | |
137 | #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ | |
138 | #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ | |
139 | #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ | |
140 | #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ | |
141 | #define HD64461_PCCCSCR_RC 0x04 /* READY change */ | |
142 | #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ | |
143 | #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ | |
144 | ||
145 | /* PCC Card Status Change Interrupt Enable Register */ | |
146 | #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ | |
6d75e650 | 147 | #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ |
1da177e4 | 148 | #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ |
6d75e650 | 149 | #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ |
1da177e4 | 150 | #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ |
6d75e650 | 151 | #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ |
1da177e4 LT |
152 | |
153 | #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ | |
154 | #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ | |
155 | #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ | |
156 | #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ | |
157 | #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ | |
158 | ||
159 | /* PCC Software Control Register */ | |
160 | #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ | |
161 | #define HD64461_PCCSCR_SWP 0x01 /* write protect */ | |
162 | ||
1da177e4 LT |
163 | #define HD64461_P0OCR 0x1202a |
164 | #define HD64461_P1OCR 0x1202c | |
165 | #define HD64461_PGCR 0x1202e | |
166 | ||
167 | #define HD64461_GPACR 0x14000 | |
168 | #define HD64461_GPBCR 0x14002 | |
169 | #define HD64461_GPCCR 0x14004 | |
170 | #define HD64461_GPDCR 0x14006 | |
171 | #define HD64461_GPADR 0x14010 | |
172 | #define HD64461_GPBDR 0x14012 | |
173 | #define HD64461_GPCDR 0x14014 | |
174 | #define HD64461_GPDDR 0x14016 | |
175 | #define HD64461_GPAICR 0x14020 | |
176 | #define HD64461_GPBICR 0x14022 | |
177 | #define HD64461_GPCICR 0x14024 | |
178 | #define HD64461_GPDICR 0x14026 | |
179 | #define HD64461_GPAISR 0x14040 | |
180 | #define HD64461_GPBISR 0x14042 | |
181 | #define HD64461_GPCISR 0x14044 | |
182 | #define HD64461_GPDISR 0x14046 | |
183 | ||
184 | #define HD64461_NIRR 0x15000 | |
185 | #define HD64461_NIMR 0x15002 | |
186 | ||
1da177e4 | 187 | #define HD64461_IRQBASE OFFCHIP_IRQ_BASE |
6d75e650 PM |
188 | #define HD64461_IRQ_NUM 16 |
189 | ||
190 | #define HD64461_IRQ_UART (HD64461_IRQBASE+5) | |
191 | #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) | |
192 | #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) | |
193 | #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) | |
194 | #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) | |
195 | #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) | |
196 | #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) | |
197 | #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) | |
198 | ||
199 | #define __IO_PREFIX hd64461 | |
200 | #include <asm/io_generic.h> | |
201 | ||
202 | /* arch/sh/cchips/hd6446x/hd64461/setup.c */ | |
203 | int hd64461_irq_demux(int irq); | |
204 | void hd64461_register_irq_demux(int irq, | |
205 | int (*demux) (int irq, void *dev), void *dev); | |
206 | void hd64461_unregister_irq_demux(int irq); | |
1da177e4 LT |
207 | |
208 | #endif |