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1da177e4 LT |
1 | #ifndef __ASM_SH_IRQ_H |
2 | #define __ASM_SH_IRQ_H | |
3 | ||
1da177e4 LT |
4 | #include <asm/machvec.h> |
5 | #include <asm/ptrace.h> /* for pt_regs */ | |
6 | ||
1da177e4 LT |
7 | /* NR_IRQS is made from three components: |
8 | * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules | |
9 | * 2. PINT_NR_IRQS - number of PINT interrupts | |
10 | * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules | |
11 | */ | |
12 | ||
13 | /* 1. ONCHIP_NR_IRQS */ | |
bf3a00f8 PM |
14 | #if defined(CONFIG_CPU_SUBTYPE_SH7604) |
15 | # define ONCHIP_NR_IRQS 24 // Actually 21 | |
16 | #elif defined(CONFIG_CPU_SUBTYPE_SH7707) | |
17 | # define ONCHIP_NR_IRQS 64 | |
18 | # define PINT_NR_IRQS 16 | |
19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7708) | |
20 | # define ONCHIP_NR_IRQS 32 | |
21 | #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | |
e5723e0e | 22 | defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
bf3a00f8 PM |
23 | defined(CONFIG_CPU_SUBTYPE_SH7705) |
24 | # define ONCHIP_NR_IRQS 64 // Actually 61 | |
25 | # define PINT_NR_IRQS 16 | |
e5723e0e PM |
26 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) |
27 | # define ONCHIP_NR_IRQS 104 | |
bf3a00f8 PM |
28 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) |
29 | # define ONCHIP_NR_IRQS 48 // Actually 44 | |
30 | #elif defined(CONFIG_CPU_SUBTYPE_SH7751) | |
31 | # define ONCHIP_NR_IRQS 72 | |
32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
33 | # define ONCHIP_NR_IRQS 112 /* XXX */ | |
34 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | |
35 | # define ONCHIP_NR_IRQS 72 | |
36 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | |
37 | # define ONCHIP_NR_IRQS 144 | |
8d27e081 | 38 | #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
e5723e0e PM |
39 | defined(CONFIG_CPU_SUBTYPE_SH73180) || \ |
40 | defined(CONFIG_CPU_SUBTYPE_SH7343) | |
bf3a00f8 | 41 | # define ONCHIP_NR_IRQS 109 |
8d27e081 PM |
42 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
43 | # define ONCHIP_NR_IRQS 111 | |
b229632a YS |
44 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
45 | # define ONCHIP_NR_IRQS 256 | |
46 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
47 | # define ONCHIP_NR_IRQS 128 | |
bf3a00f8 | 48 | #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ |
1da177e4 | 49 | # define ONCHIP_NR_IRQS 144 |
1da177e4 LT |
50 | #endif |
51 | ||
52 | /* 2. PINT_NR_IRQS */ | |
bf3a00f8 | 53 | #ifdef CONFIG_SH_UNKNOWN |
1da177e4 LT |
54 | # define PINT_NR_IRQS 16 |
55 | #else | |
56 | # ifndef PINT_NR_IRQS | |
57 | # define PINT_NR_IRQS 0 | |
58 | # endif | |
59 | #endif | |
60 | ||
61 | #if PINT_NR_IRQS > 0 | |
62 | # define PINT_IRQ_BASE ONCHIP_NR_IRQS | |
63 | #endif | |
64 | ||
65 | /* 3. OFFCHIP_NR_IRQS */ | |
bf3a00f8 PM |
66 | #if defined(CONFIG_HD64461) |
67 | # define OFFCHIP_NR_IRQS 18 | |
68 | #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */ | |
69 | # define OFFCHIP_NR_IRQS 48 | |
70 | #elif defined(CONFIG_HD64465) | |
1da177e4 | 71 | # define OFFCHIP_NR_IRQS 16 |
bf3a00f8 PM |
72 | #elif defined (CONFIG_SH_EC3104) |
73 | # define OFFCHIP_NR_IRQS 16 | |
74 | #elif defined (CONFIG_SH_DREAMCAST) | |
75 | # define OFFCHIP_NR_IRQS 96 | |
76 | #elif defined (CONFIG_SH_TITAN) | |
77 | # define OFFCHIP_NR_IRQS 4 | |
8d27e081 PM |
78 | #elif defined(CONFIG_SH_R7780RP) |
79 | # define OFFCHIP_NR_IRQS 16 | |
bc8fb5d0 PM |
80 | #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE) |
81 | # define OFFCHIP_NR_IRQS 12 | |
bf3a00f8 PM |
82 | #elif defined(CONFIG_SH_UNKNOWN) |
83 | # define OFFCHIP_NR_IRQS 16 /* Must also be last */ | |
1da177e4 | 84 | #else |
bf3a00f8 | 85 | # define OFFCHIP_NR_IRQS 0 |
1da177e4 LT |
86 | #endif |
87 | ||
88 | #if OFFCHIP_NR_IRQS > 0 | |
89 | # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS) | |
90 | #endif | |
91 | ||
92 | /* NR_IRQS. 1+2+3 */ | |
93 | #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) | |
94 | ||
1da177e4 LT |
95 | /* |
96 | * Simple Mask Register Support | |
97 | */ | |
98 | extern void make_maskreg_irq(unsigned int irq); | |
99 | extern unsigned short *irq_mask_register; | |
100 | ||
0f08f338 PM |
101 | /* |
102 | * PINT IRQs | |
103 | */ | |
104 | void init_IRQ_pint(void); | |
105 | ||
bd71ab88 JL |
106 | struct ipr_data { |
107 | unsigned int irq; | |
108 | unsigned int addr; /* Address of Interrupt Priority Register */ | |
109 | int shift; /* Shifts of the 16-bit data */ | |
110 | int priority; /* The priority */ | |
111 | }; | |
112 | ||
1da177e4 LT |
113 | /* |
114 | * Function for "on chip support modules". | |
115 | */ | |
bd71ab88 | 116 | extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); |
1da177e4 LT |
117 | extern void make_imask_irq(unsigned int irq); |
118 | ||
525ccc45 PM |
119 | struct intc2_data { |
120 | unsigned short irq; | |
121 | unsigned char ipr_offset, ipr_shift; | |
122 | unsigned char msk_offset, msk_shift; | |
123 | unsigned char priority; | |
124 | }; | |
125 | ||
66a74057 | 126 | void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs); |
1da177e4 | 127 | void init_IRQ_intc2(void); |
e5723e0e | 128 | |
1da177e4 LT |
129 | static inline int generic_irq_demux(int irq) |
130 | { | |
131 | return irq; | |
132 | } | |
133 | ||
134 | #define irq_canonicalize(irq) (irq) | |
9a7ef6d5 | 135 | #define irq_demux(irq) sh_mv.mv_irq_demux(irq) |
1da177e4 | 136 | |
a6a31139 PM |
137 | #ifdef CONFIG_4KSTACKS |
138 | extern void irq_ctx_init(int cpu); | |
139 | extern void irq_ctx_exit(int cpu); | |
140 | # define __ARCH_HAS_DO_SOFTIRQ | |
141 | #else | |
142 | # define irq_ctx_init(cpu) do { } while (0) | |
143 | # define irq_ctx_exit(cpu) do { } while (0) | |
144 | #endif | |
145 | ||
1da177e4 | 146 | #endif /* __ASM_SH_IRQ_H */ |