[deliverable/linux.git] / include / asm-sh / processor.h

/*
 * include/asm-sh/processor.h
 *
 * Copyright (C) 1999, 2000  Niibe Yutaka
 * Copyright (C) 2002, 2003  Paul Mundt
 */

#ifndef __ASM_SH_PROCESSOR_H
#define __ASM_SH_PROCESSOR_H
#ifdef __KERNEL__

#include <linux/compiler.h>
#include <asm/page.h>
#include <asm/types.h>
#include <asm/cache.h>
#include <asm/ptrace.h>
#include <asm/cpu-features.h>

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; __asm__("mova	1f, %0\n1:":"=z" (pc)); pc; })

/* Core Processor Version Register */
#define CCN_PVR		0xff000030
#define CCN_CVR		0xff000040
#define CCN_PRR		0xff000044

/*
 *  CPU type and hardware bug flags. Kept separately for each CPU.
 *
 *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
 *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
 *  for parsing the subtype in get_cpu_subtype().
 */
enum cpu_type {
	/* SH-2 types */
	CPU_SH7604,

	/* SH-3 types */
	CPU_SH7705, CPU_SH7706, CPU_SH7707,
	CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
	CPU_SH7709, CPU_SH7709A, CPU_SH7710,
	CPU_SH7729, CPU_SH7300,

	/* SH-4 types */
	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
	CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
	CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,

	/* Unknown subtype */
	CPU_SH_NONE
};

struct sh_cpuinfo {
	unsigned int type;
	unsigned long loops_per_jiffy;

	struct cache_info icache;	/* Primary I-cache */
	struct cache_info dcache;	/* Primary D-cache */
	struct cache_info scache;	/* Secondary cache */

	unsigned long flags;
} __attribute__ ((aligned(SMP_CACHE_BYTES)));

extern struct sh_cpuinfo boot_cpu_data;

#ifdef CONFIG_SMP
extern struct sh_cpuinfo cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
#else
#define cpu_data (&boot_cpu_data)
#define current_cpu_data boot_cpu_data
#endif

/*
 * User space process size: 2GB.
 *
 * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
 */
#define TASK_SIZE	0x7c000000UL

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)

/*
 * Bit of SR register
 *
 * FD-bit:
 *     When it's set, it means the processor doesn't have right to use FPU,
 *     and it results exception when the floating operation is executed.
 *
 * IMASK-bit:
 *     Interrupt level mask
 */
#define SR_FD		0x00008000
#define SR_DSP		0x00001000
#define SR_IMASK	0x000000f0

/*
 * FPU structure and data
 */

struct sh_fpu_hard_struct {
	unsigned long fp_regs[16];
	unsigned long xfp_regs[16];
	unsigned long fpscr;
	unsigned long fpul;

	long status; /* software status information */
};

/* Dummy fpu emulator  */
struct sh_fpu_soft_struct {
	unsigned long fp_regs[16];
	unsigned long xfp_regs[16];
	unsigned long fpscr;
	unsigned long fpul;

	unsigned char lookahead;
	unsigned long entry_pc;
};

union sh_fpu_union {
	struct sh_fpu_hard_struct hard;
	struct sh_fpu_soft_struct soft;
};

struct thread_struct {
	unsigned long sp;
	unsigned long pc;

	unsigned long trap_no, error_code;
	unsigned long address;
	/* Hardware debugging registers may come here */
	unsigned long ubc_pc;

	/* floating point info */
	union sh_fpu_union fpu;
};

typedef struct {
	unsigned long seg;
} mm_segment_t;

/* Count of active tasks with UBC settings */
extern int ubc_usercnt;

#define INIT_THREAD  {						\
	sizeof(init_stack) + (long) &init_stack, /* sp */	\
	0,					 /* pc */	\
	0, 0,							\
	0,							\
	0,							\
	{{{0,}},}				/* fpu state */	\
}

/*
 * Do necessary setup to start up a newly executed thread.
 */
#define start_thread(regs, new_pc, new_sp)	 \
	set_fs(USER_DS);			 \
	regs->pr = 0;				 \
	regs->sr = SR_FD;	/* User mode. */ \
	regs->pc = new_pc;			 \
	regs->regs[15] = new_sp

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

/* Prepare to copy thread state - unlazy all lazy status */
#define prepare_to_copy(tsk)	do { } while (0)

/*
 * create a kernel thread without removing it from tasklists
 */
extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);

/* Copy and release all segment info associated with a VM */
#define copy_segments(p, mm)	do { } while(0)
#define release_segments(mm)	do { } while(0)

/*
 * FPU lazy state save handling.
 */

static __inline__ void disable_fpu(void)
{
	unsigned long __dummy;

	/* Set FD flag in SR */
	__asm__ __volatile__("stc	sr, %0\n\t"
			     "or	%1, %0\n\t"
			     "ldc	%0, sr"
			     : "=&r" (__dummy)
			     : "r" (SR_FD));
}

static __inline__ void enable_fpu(void)
{
	unsigned long __dummy;

	/* Clear out FD flag in SR */
	__asm__ __volatile__("stc	sr, %0\n\t"
			     "and	%1, %0\n\t"
			     "ldc	%0, sr"
			     : "=&r" (__dummy)
			     : "r" (~SR_FD));
}

static __inline__ void release_fpu(struct pt_regs *regs)
{
	regs->sr |= SR_FD;
}

static __inline__ void grab_fpu(struct pt_regs *regs)
{
	regs->sr &= ~SR_FD;
}

#ifdef CONFIG_CPU_SH4
extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
#else
#define save_fpu(tsk)	do { } while (0)
#endif

#define unlazy_fpu(tsk, regs) do {			\
	if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) {	\
		save_fpu(tsk, regs);			\
	}						\
} while (0)

#define clear_fpu(tsk, regs) do {				\
	if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) {		\
		clear_tsk_thread_flag(tsk, TIF_USEDFPU);	\
		release_fpu(regs);				\
	}							\
} while (0)

/* Double presision, NANS as NANS, rounding to nearest, no exceptions */
#define FPSCR_INIT  0x00080000

#define	FPSCR_CAUSE_MASK	0x0001f000	/* Cause bits */
#define	FPSCR_FLAG_MASK		0x0000007c	/* Flag bits */

/*
 * Return saved PC of a blocked thread.
 */
#define thread_saved_pc(tsk)	(tsk->thread.pc)

void show_trace(struct task_struct *tsk, unsigned long *sp,
		struct pt_regs *regs);
extern unsigned long get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk)  ((tsk)->thread.pc)
#define KSTK_ESP(tsk)  ((tsk)->thread.sp)

#define cpu_sleep()	__asm__ __volatile__ ("sleep" : : : "memory")
#define cpu_relax()	barrier()

#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \
    defined(CONFIG_CPU_SH4)
#define PREFETCH_STRIDE		L1_CACHE_BYTES
#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
static inline void prefetch(void *x)
{
	__asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory");
}

#define prefetchw(x)	prefetch(x)
#endif

#ifdef CONFIG_VSYSCALL
extern int vsyscall_init(void);
#else
#define vsyscall_init() do { } while (0)
#endif

#endif /* __KERNEL__ */
#endif /* __ASM_SH_PROCESSOR_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-sh/processor.h
	3	*
	4	* Copyright (C) 1999, 2000 Niibe Yutaka
	5	* Copyright (C) 2002, 2003 Paul Mundt
	6	*/
	7
	8	#ifndef __ASM_SH_PROCESSOR_H
	9	#define __ASM_SH_PROCESSOR_H
	10	#ifdef __KERNEL__
	11
f6dc8c5b	12	#include <linux/compiler.h>
1da177e4 LT	13	#include <asm/page.h>
	14	#include <asm/types.h>
	15	#include <asm/cache.h>
1da177e4	16	#include <asm/ptrace.h>
315bb968	17	#include <asm/cpu-features.h>
1da177e4 LT	18
	19	/*
	20	* Default implementation of macro that returns current
	21	* instruction pointer ("program counter").
	22	*/
	23	#define current_text_addr() ({ void *pc; __asm__("mova 1f, %0\n1:":"=z" (pc)); pc; })
	24
	25	/* Core Processor Version Register */
	26	#define CCN_PVR 0xff000030
	27	#define CCN_CVR 0xff000040
	28	#define CCN_PRR 0xff000044
	29
	30	/*
	31	* CPU type and hardware bug flags. Kept separately for each CPU.
	32	*
	33	* Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
de02797a	34	* in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
1da177e4 LT	35	* for parsing the subtype in get_cpu_subtype().
	36	*/
	37	enum cpu_type {
	38	/* SH-2 types */
	39	CPU_SH7604,
	40
	41	/* SH-3 types */
e5723e0e PM	42	CPU_SH7705, CPU_SH7706, CPU_SH7707,
	43	CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
	44	CPU_SH7709, CPU_SH7709A, CPU_SH7710,
	45	CPU_SH7729, CPU_SH7300,
1da177e4 LT	46
	47	/* SH-4 types */
	48	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
	49	CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
e5723e0e	50	CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,
1da177e4 LT	51
	52	/* Unknown subtype */
	53	CPU_SH_NONE
	54	};
	55
	56	struct sh_cpuinfo {
72c35543	57	unsigned int type;
1da177e4 LT	58	unsigned long loops_per_jiffy;
1da177e4 LT	59
72c35543 PM	60	struct cache_info icache; /* Primary I-cache */
	61	struct cache_info dcache; /* Primary D-cache */
	62	struct cache_info scache; /* Secondary cache */
1da177e4 LT	63
1da177e4 LT	64	unsigned long flags;
72c35543	65	} __attribute__ ((aligned(SMP_CACHE_BYTES)));
1da177e4 LT	66
	67	extern struct sh_cpuinfo boot_cpu_data;
	68
	69	#ifdef CONFIG_SMP
	70	extern struct sh_cpuinfo cpu_data[];
	71	#define current_cpu_data cpu_data[smp_processor_id()]
	72	#else
	73	#define cpu_data (&boot_cpu_data)
	74	#define current_cpu_data boot_cpu_data
	75	#endif
	76
	77	/*
	78	* User space process size: 2GB.
	79	*
	80	* Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
	81	*/
	82	#define TASK_SIZE 0x7c000000UL
	83
	84	/* This decides where the kernel will search for a free chunk of vm
	85	* space during mmap's.
	86	*/
	87	#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
	88
	89	/*
	90	* Bit of SR register
	91	*
	92	* FD-bit:
	93	* When it's set, it means the processor doesn't have right to use FPU,
	94	* and it results exception when the floating operation is executed.
	95	*
	96	* IMASK-bit:
	97	* Interrupt level mask
	98	*/
	99	#define SR_FD 0x00008000
	100	#define SR_DSP 0x00001000
	101	#define SR_IMASK 0x000000f0
	102
	103	/*
	104	* FPU structure and data
	105	*/
	106
	107	struct sh_fpu_hard_struct {
	108	unsigned long fp_regs[16];
	109	unsigned long xfp_regs[16];
	110	unsigned long fpscr;
	111	unsigned long fpul;
	112
	113	long status; /* software status information */
	114	};
	115
	116	/* Dummy fpu emulator */
	117	struct sh_fpu_soft_struct {
	118	unsigned long fp_regs[16];
	119	unsigned long xfp_regs[16];
	120	unsigned long fpscr;
	121	unsigned long fpul;
	122
	123	unsigned char lookahead;
	124	unsigned long entry_pc;
	125	};
	126
	127	union sh_fpu_union {
	128	struct sh_fpu_hard_struct hard;
	129	struct sh_fpu_soft_struct soft;
130	};
131
1da177e4 LT	132	struct thread_struct {
	133	unsigned long sp;
	134	unsigned long pc;
	135
	136	unsigned long trap_no, error_code;
	137	unsigned long address;
	138	/* Hardware debugging registers may come here */
	139	unsigned long ubc_pc;
	140
	141	/* floating point info */
	142	union sh_fpu_union fpu;
	143	};
	144
2991be72 PM	145	typedef struct {
	146	unsigned long seg;
	147	} mm_segment_t;
	148
1da177e4 LT	149	/* Count of active tasks with UBC settings */
	150	extern int ubc_usercnt;
	151
	152	#define INIT_THREAD { \
	153	sizeof(init_stack) + (long) &init_stack, /* sp */ \
	154	0, /* pc */ \
de02797a PM	155	0, 0, \
	156	0, \
	157	0, \
	158	{{{0,}},} /* fpu state */ \
1da177e4 LT	159	}
	160
	161	/*
	162	* Do necessary setup to start up a newly executed thread.
	163	*/
	164	#define start_thread(regs, new_pc, new_sp) \
	165	set_fs(USER_DS); \
de02797a	166	regs->pr = 0; \
1da177e4 LT	167	regs->sr = SR_FD; /* User mode. */ \
	168	regs->pc = new_pc; \
	169	regs->regs[15] = new_sp
	170
	171	/* Forward declaration, a strange C thing */
	172	struct task_struct;
	173	struct mm_struct;
	174
	175	/* Free all resources held by a thread. */
	176	extern void release_thread(struct task_struct *);
	177
	178	/* Prepare to copy thread state - unlazy all lazy status */
	179	#define prepare_to_copy(tsk) do { } while (0)
	180
	181	/*
	182	* create a kernel thread without removing it from tasklists
	183	*/
	184	extern int kernel_thread(int (fn)(void ), void * arg, unsigned long flags);
	185
	186	/* Copy and release all segment info associated with a VM */
	187	#define copy_segments(p, mm) do { } while(0)
	188	#define release_segments(mm) do { } while(0)
	189
	190	/*
	191	* FPU lazy state save handling.
	192	*/
	193
	194	static __inline__ void disable_fpu(void)
	195	{
	196	unsigned long __dummy;
	197
	198	/* Set FD flag in SR */
	199	__asm__ __volatile__("stc sr, %0\n\t"
	200	"or %1, %0\n\t"
	201	"ldc %0, sr"
	202	: "=&r" (__dummy)
	203	: "r" (SR_FD));
	204	}
	205
	206	static __inline__ void enable_fpu(void)
	207	{
	208	unsigned long __dummy;
	209
	210	/* Clear out FD flag in SR */
	211	__asm__ __volatile__("stc sr, %0\n\t"
	212	"and %1, %0\n\t"
	213	"ldc %0, sr"
	214	: "=&r" (__dummy)
	215	: "r" (~SR_FD));
	216	}
	217
	218	static __inline__ void release_fpu(struct pt_regs *regs)
	219	{
	220	regs->sr \|= SR_FD;
	221	}
	222
	223	static __inline__ void grab_fpu(struct pt_regs *regs)
	224	{
	225	regs->sr &= ~SR_FD;
	226	}
	227
	228	#ifdef CONFIG_CPU_SH4
	229	extern void save_fpu(struct task_struct __tsk, struct pt_regs regs);
	230	#else
231	#define save_fpu(tsk) do { } while (0)
232	#endif
233
de02797a	234	#define unlazy_fpu(tsk, regs) do { \
1da177e4	235	if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
de02797a	236	save_fpu(tsk, regs); \
1da177e4 LT	237	} \
	238	} while (0)
	239
de02797a PM	240	#define clear_fpu(tsk, regs) do { \
	241	if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
	242	clear_tsk_thread_flag(tsk, TIF_USEDFPU); \
	243	release_fpu(regs); \
1da177e4 LT	244	} \
	245	} while (0)
	246
	247	/* Double presision, NANS as NANS, rounding to nearest, no exceptions */
	248	#define FPSCR_INIT 0x00080000
	249
	250	#define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */
	251	#define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */
	252
	253	/*
	254	* Return saved PC of a blocked thread.
	255	*/
	256	#define thread_saved_pc(tsk) (tsk->thread.pc)
	257
6b002230 PM	258	void show_trace(struct task_struct tsk, unsigned long sp,
6b002230 PM	259	struct pt_regs *regs);
1da177e4 LT	260	extern unsigned long get_wchan(struct task_struct *p);
	261
	262	#define KSTK_EIP(tsk) ((tsk)->thread.pc)
	263	#define KSTK_ESP(tsk) ((tsk)->thread.sp)
	264
	265	#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
f6dc8c5b	266	#define cpu_relax() barrier()
1da177e4	267
e86d6b66 PM	268	#if defined(CONFIG_CPU_SH2A) \|\| defined(CONFIG_CPU_SH3) \|\| \
	269	defined(CONFIG_CPU_SH4)
	270	#define PREFETCH_STRIDE L1_CACHE_BYTES
	271	#define ARCH_HAS_PREFETCH
	272	#define ARCH_HAS_PREFETCHW
	273	static inline void prefetch(void *x)
	274	{
	275	__asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory");
	276	}
	277
	278	#define prefetchw(x) prefetch(x)
	279	#endif
	280
19f9a34f PM	281	#ifdef CONFIG_VSYSCALL
	282	extern int vsyscall_init(void);
	283	#else
	284	#define vsyscall_init() do { } while (0)
	285	#endif
	286
1da177e4 LT	287	#endif /* __KERNEL__ */
1da177e4 LT	288	#endif /* __ASM_SH_PROCESSOR_H */