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1da177e4 | 1 | /* -------------------------------------------------------------------- */ |
adf1890b | 2 | /* voyagergx.h */ |
1da177e4 LT |
3 | /* -------------------------------------------------------------------- */ |
4 | /* This program is free software; you can redistribute it and/or modify | |
5 | it under the terms of the GNU General Public License as published by | |
6 | the Free Software Foundation; either version 2 of the License, or | |
7 | (at your option) any later version. | |
8 | ||
9 | This program is distributed in the hope that it will be useful, | |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
13 | ||
14 | You should have received a copy of the GNU General Public License | |
15 | along with this program; if not, write to the Free Software | |
16 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | ||
18 | Copyright 2003 (c) Lineo uSolutions,Inc. | |
19 | */ | |
20 | /* -------------------------------------------------------------------- */ | |
21 | ||
22 | #ifndef _VOYAGER_GX_REG_H | |
23 | #define _VOYAGER_GX_REG_H | |
24 | ||
25 | #define VOYAGER_BASE 0xb3e00000 | |
26 | #define VOYAGER_USBH_BASE (0x40000 + VOYAGER_BASE) | |
27 | #define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE) | |
28 | #define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE) | |
29 | ||
48180cab MD |
30 | #define VOYAGER_IRQ_NUM 26 |
31 | #define VOYAGER_IRQ_BASE 200 | |
32 | ||
33 | #define IRQ_SM501_UP (VOYAGER_IRQ_BASE + 0) | |
34 | #define IRQ_SM501_G54 (VOYAGER_IRQ_BASE + 1) | |
35 | #define IRQ_SM501_G53 (VOYAGER_IRQ_BASE + 2) | |
36 | #define IRQ_SM501_G52 (VOYAGER_IRQ_BASE + 3) | |
37 | #define IRQ_SM501_G51 (VOYAGER_IRQ_BASE + 4) | |
38 | #define IRQ_SM501_G50 (VOYAGER_IRQ_BASE + 5) | |
39 | #define IRQ_SM501_G49 (VOYAGER_IRQ_BASE + 6) | |
40 | #define IRQ_SM501_G48 (VOYAGER_IRQ_BASE + 7) | |
41 | #define IRQ_SM501_I2C (VOYAGER_IRQ_BASE + 8) | |
42 | #define IRQ_SM501_PW (VOYAGER_IRQ_BASE + 9) | |
43 | #define IRQ_SM501_DMA (VOYAGER_IRQ_BASE + 10) | |
44 | #define IRQ_SM501_PCI (VOYAGER_IRQ_BASE + 11) | |
45 | #define IRQ_SM501_I2S (VOYAGER_IRQ_BASE + 12) | |
46 | #define IRQ_SM501_AC (VOYAGER_IRQ_BASE + 13) | |
47 | #define IRQ_SM501_US (VOYAGER_IRQ_BASE + 14) | |
48 | #define IRQ_SM501_U1 (VOYAGER_IRQ_BASE + 15) | |
49 | #define IRQ_SM501_U0 (VOYAGER_IRQ_BASE + 16) | |
50 | #define IRQ_SM501_CV (VOYAGER_IRQ_BASE + 17) | |
51 | #define IRQ_SM501_MC (VOYAGER_IRQ_BASE + 18) | |
52 | #define IRQ_SM501_S1 (VOYAGER_IRQ_BASE + 19) | |
53 | #define IRQ_SM501_S0 (VOYAGER_IRQ_BASE + 20) | |
54 | #define IRQ_SM501_UH (VOYAGER_IRQ_BASE + 21) | |
55 | #define IRQ_SM501_2D (VOYAGER_IRQ_BASE + 22) | |
56 | #define IRQ_SM501_ZD (VOYAGER_IRQ_BASE + 23) | |
57 | #define IRQ_SM501_PV (VOYAGER_IRQ_BASE + 24) | |
58 | #define IRQ_SM501_CI (VOYAGER_IRQ_BASE + 25) | |
1da177e4 LT |
59 | |
60 | /* ----- MISC controle register ------------------------------ */ | |
61 | #define MISC_CTRL (0x000004 + VOYAGER_BASE) | |
62 | #define MISC_CTRL_USBCLK_48 (3 << 28) | |
63 | #define MISC_CTRL_USBCLK_96 (2 << 28) | |
64 | #define MISC_CTRL_USBCLK_CRYSTAL (1 << 28) | |
65 | ||
66 | /* ----- GPIO[31:0] register --------------------------------- */ | |
67 | #define GPIO_MUX_LOW (0x000008 + VOYAGER_BASE) | |
68 | #define GPIO_MUX_LOW_AC97 0x1F000000 | |
69 | #define GPIO_MUX_LOW_8051 0x0000ffff | |
70 | #define GPIO_MUX_LOW_PWM (1 << 29) | |
71 | ||
72 | /* ----- GPIO[63:32] register --------------------------------- */ | |
73 | #define GPIO_MUX_HIGH (0x00000C + VOYAGER_BASE) | |
74 | ||
75 | /* ----- DRAM controle register ------------------------------- */ | |
76 | #define DRAM_CTRL (0x000010 + VOYAGER_BASE) | |
77 | #define DRAM_CTRL_EMBEDDED (1 << 31) | |
78 | #define DRAM_CTRL_CPU_BURST_1 (0 << 28) | |
79 | #define DRAM_CTRL_CPU_BURST_2 (1 << 28) | |
80 | #define DRAM_CTRL_CPU_BURST_4 (2 << 28) | |
81 | #define DRAM_CTRL_CPU_BURST_8 (3 << 28) | |
82 | #define DRAM_CTRL_CPU_CAS_LATENCY (1 << 27) | |
83 | #define DRAM_CTRL_CPU_SIZE_2 (0 << 24) | |
84 | #define DRAM_CTRL_CPU_SIZE_4 (1 << 24) | |
85 | #define DRAM_CTRL_CPU_SIZE_64 (4 << 24) | |
86 | #define DRAM_CTRL_CPU_SIZE_32 (5 << 24) | |
87 | #define DRAM_CTRL_CPU_SIZE_16 (6 << 24) | |
88 | #define DRAM_CTRL_CPU_SIZE_8 (7 << 24) | |
89 | #define DRAM_CTRL_CPU_COLUMN_SIZE_1024 (0 << 22) | |
90 | #define DRAM_CTRL_CPU_COLUMN_SIZE_512 (2 << 22) | |
91 | #define DRAM_CTRL_CPU_COLUMN_SIZE_256 (3 << 22) | |
92 | #define DRAM_CTRL_CPU_ACTIVE_PRECHARGE (1 << 21) | |
93 | #define DRAM_CTRL_CPU_RESET (1 << 20) | |
94 | #define DRAM_CTRL_CPU_BANKS (1 << 19) | |
95 | #define DRAM_CTRL_CPU_WRITE_PRECHARGE (1 << 18) | |
96 | #define DRAM_CTRL_BLOCK_WRITE (1 << 17) | |
97 | #define DRAM_CTRL_REFRESH_COMMAND (1 << 16) | |
98 | #define DRAM_CTRL_SIZE_4 (0 << 13) | |
99 | #define DRAM_CTRL_SIZE_8 (1 << 13) | |
100 | #define DRAM_CTRL_SIZE_16 (2 << 13) | |
101 | #define DRAM_CTRL_SIZE_32 (3 << 13) | |
102 | #define DRAM_CTRL_SIZE_64 (4 << 13) | |
103 | #define DRAM_CTRL_SIZE_2 (5 << 13) | |
104 | #define DRAM_CTRL_COLUMN_SIZE_256 (0 << 11) | |
105 | #define DRAM_CTRL_COLUMN_SIZE_512 (2 << 11) | |
106 | #define DRAM_CTRL_COLUMN_SIZE_1024 (3 << 11) | |
107 | #define DRAM_CTRL_BLOCK_WRITE_TIME (1 << 10) | |
108 | #define DRAM_CTRL_BLOCK_WRITE_PRECHARGE (1 << 9) | |
109 | #define DRAM_CTRL_ACTIVE_PRECHARGE (1 << 8) | |
110 | #define DRAM_CTRL_RESET (1 << 7) | |
111 | #define DRAM_CTRL_REMAIN_ACTIVE (1 << 6) | |
112 | #define DRAM_CTRL_BANKS (1 << 1) | |
113 | #define DRAM_CTRL_WRITE_PRECHARGE (1 << 0) | |
114 | ||
115 | /* ----- Arvitration control register -------------------------- */ | |
116 | #define ARBITRATION_CTRL (0x000014 + VOYAGER_BASE) | |
117 | #define ARBITRATION_CTRL_CPUMEM (1 << 29) | |
118 | #define ARBITRATION_CTRL_INTMEM (1 << 28) | |
119 | #define ARBITRATION_CTRL_USB_OFF (0 << 24) | |
120 | #define ARBITRATION_CTRL_USB_PRIORITY_1 (1 << 24) | |
121 | #define ARBITRATION_CTRL_USB_PRIORITY_2 (2 << 24) | |
122 | #define ARBITRATION_CTRL_USB_PRIORITY_3 (3 << 24) | |
123 | #define ARBITRATION_CTRL_USB_PRIORITY_4 (4 << 24) | |
124 | #define ARBITRATION_CTRL_USB_PRIORITY_5 (5 << 24) | |
125 | #define ARBITRATION_CTRL_USB_PRIORITY_6 (6 << 24) | |
126 | #define ARBITRATION_CTRL_USB_PRIORITY_7 (7 << 24) | |
127 | #define ARBITRATION_CTRL_PANEL_OFF (0 << 20) | |
128 | #define ARBITRATION_CTRL_PANEL_PRIORITY_1 (1 << 20) | |
129 | #define ARBITRATION_CTRL_PANEL_PRIORITY_2 (2 << 20) | |
130 | #define ARBITRATION_CTRL_PANEL_PRIORITY_3 (3 << 20) | |
131 | #define ARBITRATION_CTRL_PANEL_PRIORITY_4 (4 << 20) | |
132 | #define ARBITRATION_CTRL_PANEL_PRIORITY_5 (5 << 20) | |
133 | #define ARBITRATION_CTRL_PANEL_PRIORITY_6 (6 << 20) | |
134 | #define ARBITRATION_CTRL_PANEL_PRIORITY_7 (7 << 20) | |
135 | #define ARBITRATION_CTRL_ZVPORT_OFF (0 << 16) | |
136 | #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_1 (1 << 16) | |
137 | #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_2 (2 << 16) | |
138 | #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_3 (3 << 16) | |
139 | #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_4 (4 << 16) | |
140 | #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_5 (5 << 16) | |
141 | #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_6 (6 << 16) | |
142 | #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_7 (7 << 16) | |
143 | #define ARBITRATION_CTRL_CMD_INTPR_OFF (0 << 12) | |
144 | #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 (1 << 12) | |
145 | #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_2 (2 << 12) | |
146 | #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_3 (3 << 12) | |
147 | #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_4 (4 << 12) | |
148 | #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_5 (5 << 12) | |
149 | #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_6 (6 << 12) | |
150 | #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_7 (7 << 12) | |
151 | #define ARBITRATION_CTRL_DMA_OFF (0 << 8) | |
152 | #define ARBITRATION_CTRL_DMA_PRIORITY_1 (1 << 8) | |
153 | #define ARBITRATION_CTRL_DMA_PRIORITY_2 (2 << 8) | |
154 | #define ARBITRATION_CTRL_DMA_PRIORITY_3 (3 << 8) | |
155 | #define ARBITRATION_CTRL_DMA_PRIORITY_4 (4 << 8) | |
156 | #define ARBITRATION_CTRL_DMA_PRIORITY_5 (5 << 8) | |
157 | #define ARBITRATION_CTRL_DMA_PRIORITY_6 (6 << 8) | |
158 | #define ARBITRATION_CTRL_DMA_PRIORITY_7 (7 << 8) | |
159 | #define ARBITRATION_CTRL_VIDEO_OFF (0 << 4) | |
160 | #define ARBITRATION_CTRL_VIDEO_PRIORITY_1 (1 << 4) | |
161 | #define ARBITRATION_CTRL_VIDEO_PRIORITY_2 (2 << 4) | |
162 | #define ARBITRATION_CTRL_VIDEO_PRIORITY_3 (3 << 4) | |
163 | #define ARBITRATION_CTRL_VIDEO_PRIORITY_4 (4 << 4) | |
164 | #define ARBITRATION_CTRL_VIDEO_PRIORITY_5 (5 << 4) | |
165 | #define ARBITRATION_CTRL_VIDEO_PRIORITY_6 (6 << 4) | |
166 | #define ARBITRATION_CTRL_VIDEO_PRIORITY_7 (7 << 4) | |
167 | #define ARBITRATION_CTRL_CRT_OFF (0 << 0) | |
168 | #define ARBITRATION_CTRL_CRT_PRIORITY_1 (1 << 0) | |
169 | #define ARBITRATION_CTRL_CRT_PRIORITY_2 (2 << 0) | |
170 | #define ARBITRATION_CTRL_CRT_PRIORITY_3 (3 << 0) | |
171 | #define ARBITRATION_CTRL_CRT_PRIORITY_4 (4 << 0) | |
172 | #define ARBITRATION_CTRL_CRT_PRIORITY_5 (5 << 0) | |
173 | #define ARBITRATION_CTRL_CRT_PRIORITY_6 (6 << 0) | |
174 | #define ARBITRATION_CTRL_CRT_PRIORITY_7 (7 << 0) | |
175 | ||
176 | /* ----- Command list status register -------------------------- */ | |
177 | #define CMD_INTPR_STATUS (0x000024 + VOYAGER_BASE) | |
178 | ||
179 | /* ----- Interrupt status register ----------------------------- */ | |
180 | #define INT_STATUS (0x00002c + VOYAGER_BASE) | |
181 | #define INT_STATUS_UH (1 << 6) | |
182 | #define INT_STATUS_MC (1 << 10) | |
183 | #define INT_STATUS_U0 (1 << 12) | |
184 | #define INT_STATUS_U1 (1 << 13) | |
185 | #define INT_STATUS_AC (1 << 17) | |
186 | ||
187 | /* ----- Interrupt mask register ------------------------------ */ | |
188 | #define VOYAGER_INT_MASK (0x000030 + VOYAGER_BASE) | |
189 | #define VOYAGER_INT_MASK_AC (1 << 17) | |
190 | ||
191 | /* ----- Current Gate register ---------------------------------*/ | |
192 | #define CURRENT_GATE (0x000038 + VOYAGER_BASE) | |
193 | ||
194 | /* ----- Power mode 0 gate register --------------------------- */ | |
195 | #define POWER_MODE0_GATE (0x000040 + VOYAGER_BASE) | |
196 | #define POWER_MODE0_GATE_G (1 << 6) | |
197 | #define POWER_MODE0_GATE_U0 (1 << 7) | |
198 | #define POWER_MODE0_GATE_U1 (1 << 8) | |
199 | #define POWER_MODE0_GATE_UH (1 << 11) | |
200 | #define POWER_MODE0_GATE_AC (1 << 18) | |
201 | ||
202 | /* ----- Power mode 1 gate register --------------------------- */ | |
203 | #define POWER_MODE1_GATE (0x000048 + VOYAGER_BASE) | |
204 | #define POWER_MODE1_GATE_G (1 << 6) | |
205 | #define POWER_MODE1_GATE_U0 (1 << 7) | |
206 | #define POWER_MODE1_GATE_U1 (1 << 8) | |
207 | #define POWER_MODE1_GATE_UH (1 << 11) | |
208 | #define POWER_MODE1_GATE_AC (1 << 18) | |
209 | ||
210 | /* ----- Power mode 0 clock register -------------------------- */ | |
211 | #define POWER_MODE0_CLOCK (0x000044 + VOYAGER_BASE) | |
212 | ||
213 | /* ----- Power mode 1 clock register -------------------------- */ | |
214 | #define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE) | |
215 | ||
216 | /* ----- Power mode controll register ------------------------- */ | |
217 | #define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE) | |
218 | ||
219 | /* ----- Miscellaneous Timing register ------------------------ */ | |
220 | #define SYSTEM_DRAM_CTRL (0x000068 + VOYAGER_BASE) | |
221 | ||
222 | /* ----- PWM register ------------------------------------------*/ | |
223 | #define PWM_0 (0x010020 + VOYAGER_BASE) | |
224 | #define PWM_0_HC(x) (((x)&0x0fff)<<20) | |
225 | #define PWM_0_LC(x) (((x)&0x0fff)<<8 ) | |
226 | #define PWM_0_CLK_DEV(x) (((x)&0x000f)<<4 ) | |
227 | #define PWM_0_EN (1<<0) | |
228 | ||
229 | /* ----- I2C register ----------------------------------------- */ | |
230 | #define I2C_BYTECOUNT (0x010040 + VOYAGER_BASE) | |
231 | #define I2C_CONTROL (0x010041 + VOYAGER_BASE) | |
232 | #define I2C_STATUS (0x010042 + VOYAGER_BASE) | |
233 | #define I2C_RESET (0x010042 + VOYAGER_BASE) | |
234 | #define I2C_SADDRESS (0x010043 + VOYAGER_BASE) | |
235 | #define I2C_DATA (0x010044 + VOYAGER_BASE) | |
236 | ||
237 | /* ----- Controle register bits ----------------------------------------- */ | |
238 | #define I2C_CONTROL_E (1 << 0) | |
239 | #define I2C_CONTROL_MODE (1 << 1) | |
240 | #define I2C_CONTROL_STATUS (1 << 2) | |
241 | #define I2C_CONTROL_INT (1 << 4) | |
242 | #define I2C_CONTROL_INTACK (1 << 5) | |
243 | #define I2C_CONTROL_REPEAT (1 << 6) | |
244 | ||
245 | /* ----- Status register bits ----------------------------------------- */ | |
246 | #define I2C_STATUS_BUSY (1 << 0) | |
247 | #define I2C_STATUS_ACK (1 << 1) | |
248 | #define I2C_STATUS_ERROR (1 << 2) | |
249 | #define I2C_STATUS_COMPLETE (1 << 3) | |
250 | ||
251 | /* ----- Reset register ---------------------------------------------- */ | |
252 | #define I2C_RESET_ERROR (1 << 2) | |
253 | ||
254 | /* ----- transmission frequencies ------------------------------------- */ | |
255 | #define I2C_SADDRESS_SELECT (1 << 0) | |
256 | ||
257 | /* ----- Display Controll register ----------------------------------------- */ | |
258 | #define PANEL_DISPLAY_CTRL (0x080000 + VOYAGER_BASE) | |
259 | #define PANEL_DISPLAY_CTRL_BIAS (1<<26) | |
260 | #define PANEL_PAN_CTRL (0x080004 + VOYAGER_BASE) | |
261 | #define PANEL_COLOR_KEY (0x080008 + VOYAGER_BASE) | |
262 | #define PANEL_FB_ADDRESS (0x08000C + VOYAGER_BASE) | |
263 | #define PANEL_FB_WIDTH (0x080010 + VOYAGER_BASE) | |
264 | #define PANEL_WINDOW_WIDTH (0x080014 + VOYAGER_BASE) | |
265 | #define PANEL_WINDOW_HEIGHT (0x080018 + VOYAGER_BASE) | |
266 | #define PANEL_PLANE_TL (0x08001C + VOYAGER_BASE) | |
267 | #define PANEL_PLANE_BR (0x080020 + VOYAGER_BASE) | |
268 | #define PANEL_HORIZONTAL_TOTAL (0x080024 + VOYAGER_BASE) | |
269 | #define PANEL_HORIZONTAL_SYNC (0x080028 + VOYAGER_BASE) | |
270 | #define PANEL_VERTICAL_TOTAL (0x08002C + VOYAGER_BASE) | |
271 | #define PANEL_VERTICAL_SYNC (0x080030 + VOYAGER_BASE) | |
272 | #define PANEL_CURRENT_LINE (0x080034 + VOYAGER_BASE) | |
273 | #define VIDEO_DISPLAY_CTRL (0x080040 + VOYAGER_BASE) | |
274 | #define VIDEO_FB_0_ADDRESS (0x080044 + VOYAGER_BASE) | |
275 | #define VIDEO_FB_WIDTH (0x080048 + VOYAGER_BASE) | |
276 | #define VIDEO_FB_0_LAST_ADDRESS (0x08004C + VOYAGER_BASE) | |
277 | #define VIDEO_PLANE_TL (0x080050 + VOYAGER_BASE) | |
278 | #define VIDEO_PLANE_BR (0x080054 + VOYAGER_BASE) | |
279 | #define VIDEO_SCALE (0x080058 + VOYAGER_BASE) | |
280 | #define VIDEO_INITIAL_SCALE (0x08005C + VOYAGER_BASE) | |
281 | #define VIDEO_YUV_CONSTANTS (0x080060 + VOYAGER_BASE) | |
282 | #define VIDEO_FB_1_ADDRESS (0x080064 + VOYAGER_BASE) | |
283 | #define VIDEO_FB_1_LAST_ADDRESS (0x080068 + VOYAGER_BASE) | |
284 | #define VIDEO_ALPHA_DISPLAY_CTRL (0x080080 + VOYAGER_BASE) | |
285 | #define VIDEO_ALPHA_FB_ADDRESS (0x080084 + VOYAGER_BASE) | |
286 | #define VIDEO_ALPHA_FB_WIDTH (0x080088 + VOYAGER_BASE) | |
287 | #define VIDEO_ALPHA_FB_LAST_ADDRESS (0x08008C + VOYAGER_BASE) | |
288 | #define VIDEO_ALPHA_PLANE_TL (0x080090 + VOYAGER_BASE) | |
289 | #define VIDEO_ALPHA_PLANE_BR (0x080094 + VOYAGER_BASE) | |
290 | #define VIDEO_ALPHA_SCALE (0x080098 + VOYAGER_BASE) | |
291 | #define VIDEO_ALPHA_INITIAL_SCALE (0x08009C + VOYAGER_BASE) | |
292 | #define VIDEO_ALPHA_CHROMA_KEY (0x0800A0 + VOYAGER_BASE) | |
293 | #define PANEL_HWC_ADDRESS (0x0800F0 + VOYAGER_BASE) | |
294 | #define PANEL_HWC_LOCATION (0x0800F4 + VOYAGER_BASE) | |
295 | #define PANEL_HWC_COLOR_12 (0x0800F8 + VOYAGER_BASE) | |
296 | #define PANEL_HWC_COLOR_3 (0x0800FC + VOYAGER_BASE) | |
297 | #define ALPHA_DISPLAY_CTRL (0x080100 + VOYAGER_BASE) | |
298 | #define ALPHA_FB_ADDRESS (0x080104 + VOYAGER_BASE) | |
299 | #define ALPHA_FB_WIDTH (0x080108 + VOYAGER_BASE) | |
300 | #define ALPHA_PLANE_TL (0x08010C + VOYAGER_BASE) | |
301 | #define ALPHA_PLANE_BR (0x080110 + VOYAGER_BASE) | |
302 | #define ALPHA_CHROMA_KEY (0x080114 + VOYAGER_BASE) | |
303 | #define CRT_DISPLAY_CTRL (0x080200 + VOYAGER_BASE) | |
304 | #define CRT_FB_ADDRESS (0x080204 + VOYAGER_BASE) | |
305 | #define CRT_FB_WIDTH (0x080208 + VOYAGER_BASE) | |
306 | #define CRT_HORIZONTAL_TOTAL (0x08020C + VOYAGER_BASE) | |
307 | #define CRT_HORIZONTAL_SYNC (0x080210 + VOYAGER_BASE) | |
308 | #define CRT_VERTICAL_TOTAL (0x080214 + VOYAGER_BASE) | |
309 | #define CRT_VERTICAL_SYNC (0x080218 + VOYAGER_BASE) | |
310 | #define CRT_SIGNATURE_ANALYZER (0x08021C + VOYAGER_BASE) | |
311 | #define CRT_CURRENT_LINE (0x080220 + VOYAGER_BASE) | |
312 | #define CRT_MONITOR_DETECT (0x080224 + VOYAGER_BASE) | |
313 | #define CRT_HWC_ADDRESS (0x080230 + VOYAGER_BASE) | |
314 | #define CRT_HWC_LOCATION (0x080234 + VOYAGER_BASE) | |
315 | #define CRT_HWC_COLOR_12 (0x080238 + VOYAGER_BASE) | |
316 | #define CRT_HWC_COLOR_3 (0x08023C + VOYAGER_BASE) | |
317 | #define CRT_PALETTE_RAM (0x080400 + VOYAGER_BASE) | |
318 | #define PANEL_PALETTE_RAM (0x080800 + VOYAGER_BASE) | |
319 | #define VIDEO_PALETTE_RAM (0x080C00 + VOYAGER_BASE) | |
320 | ||
321 | /* ----- 8051 Controle register ----------------------------------------- */ | |
322 | #define VOYAGER_8051_BASE (0x000c0000 + VOYAGER_BASE) | |
323 | #define VOYAGER_8051_RESET (0x000b0000 + VOYAGER_BASE) | |
324 | #define VOYAGER_8051_SELECT (0x000b0004 + VOYAGER_BASE) | |
325 | #define VOYAGER_8051_CPU_INT (0x000b000c + VOYAGER_BASE) | |
326 | ||
327 | /* ----- AC97 Controle register ----------------------------------------- */ | |
328 | #define AC97_TX_SLOT0 (0x00000000 + VOYAGER_AC97_BASE) | |
329 | #define AC97_CONTROL_STATUS (0x00000080 + VOYAGER_AC97_BASE) | |
330 | #define AC97C_READ (1 << 19) | |
331 | #define AC97C_WD_BIT (1 << 2) | |
332 | #define AC97C_INDEX_MASK 0x7f | |
9c57548f PM |
333 | |
334 | /* arch/sh/cchips/voyagergx/consistent.c */ | |
335 | void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t); | |
336 | int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t); | |
1da177e4 | 337 | |
48180cab MD |
338 | /* arch/sh/cchips/voyagergx/irq.c */ |
339 | void setup_voyagergx_irq(void); | |
340 | ||
1da177e4 | 341 | #endif /* _VOYAGER_GX_REG_H */ |