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1 | #ifndef __ASM_SH64_IRQ_H |
2 | #define __ASM_SH64_IRQ_H | |
3 | ||
4 | /* | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file "COPYING" in the main directory of this archive | |
7 | * for more details. | |
8 | * | |
9 | * include/asm-sh64/irq.h | |
10 | * | |
11 | * Copyright (C) 2000, 2001 Paolo Alberelli | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/config.h> | |
16 | ||
17 | /* | |
18 | * Encoded IRQs are not considered worth to be supported. | |
19 | * Main reason is that there's no per-encoded-interrupt | |
20 | * enable/disable mechanism (as there was in SH3/4). | |
21 | * An all enabled/all disabled is worth only if there's | |
22 | * a cascaded IC to disable/enable/ack on. Until such | |
23 | * IC is available there's no such support. | |
24 | * | |
25 | * Presumably Encoded IRQs may use extra IRQs beyond 64, | |
26 | * below. Some logic must be added to cope with IRQ_IRL? | |
27 | * in an exclusive way. | |
28 | * | |
29 | * Priorities are set at Platform level, when IRQ_IRL0-3 | |
30 | * are set to 0 Encoding is allowed. Otherwise it's not | |
31 | * allowed. | |
32 | */ | |
33 | ||
34 | /* Independent IRQs */ | |
35 | #define IRQ_IRL0 0 | |
36 | #define IRQ_IRL1 1 | |
37 | #define IRQ_IRL2 2 | |
38 | #define IRQ_IRL3 3 | |
39 | ||
40 | #define IRQ_INTA 4 | |
41 | #define IRQ_INTB 5 | |
42 | #define IRQ_INTC 6 | |
43 | #define IRQ_INTD 7 | |
44 | ||
45 | #define IRQ_SERR 12 | |
46 | #define IRQ_ERR 13 | |
47 | #define IRQ_PWR3 14 | |
48 | #define IRQ_PWR2 15 | |
49 | #define IRQ_PWR1 16 | |
50 | #define IRQ_PWR0 17 | |
51 | ||
52 | #define IRQ_DMTE0 18 | |
53 | #define IRQ_DMTE1 19 | |
54 | #define IRQ_DMTE2 20 | |
55 | #define IRQ_DMTE3 21 | |
56 | #define IRQ_DAERR 22 | |
57 | ||
58 | #define IRQ_TUNI0 32 | |
59 | #define IRQ_TUNI1 33 | |
60 | #define IRQ_TUNI2 34 | |
61 | #define IRQ_TICPI2 35 | |
62 | ||
63 | #define IRQ_ATI 36 | |
64 | #define IRQ_PRI 37 | |
65 | #define IRQ_CUI 38 | |
66 | ||
67 | #define IRQ_ERI 39 | |
68 | #define IRQ_RXI 40 | |
69 | #define IRQ_BRI 41 | |
70 | #define IRQ_TXI 42 | |
71 | ||
72 | #define IRQ_ITI 63 | |
73 | ||
74 | #define NR_INTC_IRQS 64 | |
75 | ||
76 | #ifdef CONFIG_SH_CAYMAN | |
77 | #define NR_EXT_IRQS 32 | |
78 | #define START_EXT_IRQS 64 | |
79 | ||
80 | /* PCI bus 2 uses encoded external interrupts on the Cayman board */ | |
81 | #define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0) | |
82 | #define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1) | |
83 | #define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2) | |
84 | #define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3) | |
85 | ||
86 | #define I8042_KBD_IRQ (START_EXT_IRQS + 2) | |
87 | #define I8042_AUX_IRQ (START_EXT_IRQS + 6) | |
88 | ||
89 | #define IRQ_CFCARD (START_EXT_IRQS + 7) | |
90 | #define IRQ_PCMCIA (0) | |
91 | ||
92 | #else | |
93 | #define NR_EXT_IRQS 0 | |
94 | #endif | |
95 | ||
96 | #define NR_IRQS (NR_INTC_IRQS+NR_EXT_IRQS) | |
97 | ||
98 | ||
99 | /* Default IRQs, fixed */ | |
100 | #define TIMER_IRQ IRQ_TUNI0 | |
101 | #define RTC_IRQ IRQ_CUI | |
102 | ||
103 | /* Default Priorities, Platform may choose differently */ | |
104 | #define NO_PRIORITY 0 /* Disabled */ | |
105 | #define TIMER_PRIORITY 2 | |
106 | #define RTC_PRIORITY TIMER_PRIORITY | |
107 | #define SCIF_PRIORITY 3 | |
108 | #define INTD_PRIORITY 3 | |
109 | #define IRL3_PRIORITY 4 | |
110 | #define INTC_PRIORITY 6 | |
111 | #define IRL2_PRIORITY 7 | |
112 | #define INTB_PRIORITY 9 | |
113 | #define IRL1_PRIORITY 10 | |
114 | #define INTA_PRIORITY 12 | |
115 | #define IRL0_PRIORITY 13 | |
116 | #define TOP_PRIORITY 15 | |
117 | ||
118 | extern void disable_irq(unsigned int); | |
119 | extern void disable_irq_nosync(unsigned int); | |
120 | extern void enable_irq(unsigned int); | |
121 | ||
122 | extern int intc_evt_to_irq[(0xE20/0x20)+1]; | |
123 | int intc_irq_describe(char* p, int irq); | |
124 | ||
125 | #define irq_canonicalize(irq) (irq) | |
126 | ||
127 | #ifdef CONFIG_SH_CAYMAN | |
128 | int cayman_irq_demux(int evt); | |
129 | int cayman_irq_describe(char* p, int irq); | |
130 | #define irq_demux(x) cayman_irq_demux(x) | |
131 | #define irq_describe(p, x) cayman_irq_describe(p, x) | |
132 | #else | |
133 | #define irq_demux(x) (intc_evt_to_irq[x]) | |
134 | #define irq_describe(p, x) intc_irq_describe(p, x) | |
135 | #endif | |
136 | ||
137 | /* | |
138 | * Function for "on chip support modules". | |
139 | */ | |
140 | ||
141 | /* | |
142 | * SH-5 supports Priority based interrupts only. | |
143 | * Interrupt priorities are defined at platform level. | |
144 | */ | |
145 | #define set_ipr_data(a, b, c, d) | |
146 | #define make_ipr_irq(a) | |
147 | #define make_imask_irq(a) | |
148 | ||
149 | #endif /* __ASM_SH64_IRQ_H */ |