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1da177e4 LT |
1 | /* $Id: apb.h,v 1.2 1998/04/01 20:41:49 ecd Exp $ |
2 | * apb.h: Advanced PCI Bridge Configuration Registers and Bits | |
3 | * | |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
5 | */ | |
6 | ||
7 | #ifndef _SPARC64_APB_H | |
8 | #define _SPARC64_APB_H | |
9 | ||
10 | #define APB_TICK_REGISTER 0xb0 | |
11 | #define APB_INT_ACK 0xb8 | |
12 | #define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0 | |
13 | #define APB_DMA_ASFR 0xc8 | |
14 | #define APB_DMA_AFAR 0xd0 | |
15 | #define APB_PIO_TARGET_RETRY_LIMIT 0xd8 | |
16 | #define APB_PIO_TARGET_LATENCY_TIMER 0xd9 | |
17 | #define APB_DMA_TARGET_RETRY_LIMIT 0xda | |
18 | #define APB_DMA_TARGET_LATENCY_TIMER 0xdb | |
19 | #define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc | |
20 | #define APB_SECONDARY_CONTROL 0xdd | |
21 | #define APB_IO_ADDRESS_MAP 0xde | |
22 | #define APB_MEM_ADDRESS_MAP 0xdf | |
23 | ||
24 | #define APB_PCI_CONTROL_LOW 0xe0 | |
25 | # define APB_PCI_CTL_LOW_ARB_PARK (1 << 21) | |
26 | # define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8) | |
27 | ||
28 | #define APB_PCI_CONTROL_HIGH 0xe4 | |
29 | # define APB_PCI_CTL_HIGH_SERR (1 << 2) | |
30 | # define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0) | |
31 | ||
32 | #define APB_PIO_ASFR 0xe8 | |
33 | #define APB_PIO_AFAR 0xf0 | |
34 | #define APB_DIAG_REGISTER 0xf8 | |
35 | ||
36 | #endif /* !(_SPARC64_APB_H) */ |